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1. 发明授权

US09018995B2 Integrated clock gating cell for circuits with double edge triggered flip-flops 有权
标题翻译：用于具有双边沿触发的触发器的电路的集成时钟门控单元
公开(公告)号：US09018995B2
公开(公告)日：2015-04-28
申请号：US12630260
申请日：2009-12-03
申请人： Kumar Subramani , Radu Zlatanovici
发明人： Kumar Subramani , Radu Zlatanovici
IPC分类号： H03K3/00 , H03K3/356 , H03K3/012
CPC分类号： H03K3/356156 , H03K3/012
摘要： A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.
摘要翻译：双边沿触发电路包括响应于时钟信号的时钟选通器和用于输出门控时钟信号的使能信号，响应于门控时钟信号而启动数据信号的第一双边沿触发触发器，以及第二双触发电路边沿触发触发器，其响应于时钟信号捕获数据信号，其中当使能信号处于第一逻辑状态时，时钟门控将门控时钟信号停止在第一逻辑值，并且时钟门控器将门控时钟当使能信号处于第二逻辑状态时，在下一个时钟沿从第一逻辑值发送信号。

2. 发明申请

US20070183185A1 FINFET-BASED SRAM WITH FEEDBACK 审中-公开
标题翻译：具有反馈功能的基于FINFET的SRAM
公开(公告)号：US20070183185A1
公开(公告)日：2007-08-09
申请号：US11622305
申请日：2007-01-11
申请人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
发明人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785
摘要： Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.
摘要翻译：当前体硅Si MOSFET中的固有变化和具有挑战性的泄漏控制迫使不需要的折衷，并限制了SRAM电路的缩放。本文教导了改善SRAM单元中的泄漏和噪声容限的电路和机构，例如包括六晶体管（6-T）SRAM单元设计或四晶体管（4-T）SRAM单元设计）的那些。本发明的SRAM单元利用将存储节点的一部分耦合到存取晶体管的后栅极的反馈装置。反馈优选以这种方式耦合到两个存取晶体管。使用这种内置反馈设计的SRAM单元实现了细胞静态噪声容限（SNM）的显着改进，无区域损失。反馈方案的使用还导致创建了实用的基于4-T FinFET的SRAM单元，其实现了每个100pA的每个电池的待机电流，并且具有与具有反馈的6-T电池相似的SNM改进。

3. 发明授权

US08341567B1 Boolean satisfiability based verification of analog circuits 有权
标题翻译：基于布尔可满足性的模拟电路验证
公开(公告)号：US08341567B1
公开(公告)日：2012-12-25
申请号：US12345449
申请日：2008-12-29
申请人： Saurabh K. Tiwary , Anubhav Gupta , Joel R. Phillips , Claudio Pinello , Radu Zlatanovici
发明人： Saurabh K. Tiwary , Anubhav Gupta , Joel R. Phillips , Claudio Pinello , Radu Zlatanovici
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/504
摘要： A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; converting each region determined to have a searched for combination of current and voltage values to multiple respective smaller regions; and repeating the acts of searching and converting until regions are obtained that meet the received search accuracy criteria.
摘要翻译：提供了一种用于正式验证电路设计的属性的方法，包括：接收电路的至少一部分的描述; 接收搜索精度准则的指示; 接收电路中的一个或多个设备的电流和电压之间的关系（I-V关系）的描述; 将每个I-V关系转换成这种I-V关系的保守近似值; 将电压标签分配给指示符合KVL的一个或多个终端之间的电压关系的一个或多个识别设备的一个或多个终端; 定义与KCL一致的所识别设备中的一个或多个的一个或多个相应电流集合中的相应电流关系; 搜索在每个保守近似的至少一个区域内并且与电压标签一致并且与每个相应限定的电流关系一致的电流和电压值的一个或多个组合; 将确定为将搜索到的电流和电压值的组合的每个区域转换为多个相应的较小区域; 并重复搜索和转换的行为，直到获得满足所接收到的搜索精度标准的区域。

4. 发明申请

US20100148836A1 Contention-Free Level Converting Flip-Flops for Low-Swing Clocking 有权
标题翻译：无跳跃级别转换触发器用于低摆频时钟
公开(公告)号：US20100148836A1
公开(公告)日：2010-06-17
申请号：US12335481
申请日：2008-12-15
申请人： Radu Zlatanovici
发明人： Radu Zlatanovici
IPC分类号： H03K3/00 , G06F17/50
CPC分类号： H03K3/356165 , G06F17/505
摘要： The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.
摘要翻译：本发明包括一系列电平转换触发器，其在较低电压电平下接收数据和时钟输入，同时产生较高电压电平的数据输出。这些触发器使得能够进行细粒度双电源电压技术，例如低摆频时钟（以较低电压电平分配时钟信号）和集群电压缩放（CVS）。通过在触发器中共享正反馈以进行存储和电平转换，以非常有效的方式实现电平转换。另外，所提供的触发器是无竞争的和非比例的，因此由于电平转换功能而降低了定时和功率开销。

5. 发明授权

US09071238B2 Contention-free level converting flip-flops for low-swing clocking 有权
标题翻译：无跳跃电平转换触发器，用于低频时钟
公开(公告)号：US09071238B2
公开(公告)日：2015-06-30
申请号：US12335481
申请日：2008-12-15
申请人： Radu Zlatanovici
发明人： Radu Zlatanovici
IPC分类号： H03K3/00 , H03K3/356 , G06F17/50
CPC分类号： H03K3/356165 , G06F17/505
摘要： The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.
摘要翻译：本发明包括一系列电平转换触发器，其在较低电压电平下接收数据和时钟输入，同时产生较高电压电平的数据输出。这些触发器使得能够进行细粒度双电源电压技术，例如低摆频时钟（以较低电压电平分配时钟信号）和集群电压缩放（CVS）。通过在触发器中共享正反馈以进行存储和电平转换，以非常有效的方式实现电平转换。另外，所提供的触发器是无竞争的和非比例的，因此由于电平转换功能而降低了定时和功率开销。

6. 发明授权

US08887110B1 Methods for designing intergrated circuits with automatically synthesized clock distribution networks 有权
标题翻译：用自动合成时钟分配网络设计集成电路的方法
公开(公告)号：US08887110B1
公开(公告)日：2014-11-11
申请号：US13489411
申请日：2012-06-05
申请人： Radu Zlatanovici , Christoph Albrecht , Saurabh Kumar Tiwary
发明人： Radu Zlatanovici , Christoph Albrecht , Saurabh Kumar Tiwary
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F2217/62
摘要： In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.
摘要翻译：在本发明的一个实施例中，公开了一种用于设计集成电路的方法。该方法包括将集成电路设计的时钟信宿自动分为多个分区; 自动将时钟树从主时钟发生器合成到多个分区中，以最小化多个分区内的每个分区内的本地时钟偏移; 并且将时钟去偏移电路自动合成到多个分区中的每一个中以控制相邻分区之间的时钟偏移。

7. 发明授权

US08205182B1 Automatic synthesis of clock distribution networks 有权
标题翻译：自动合成时钟分配网络
公开(公告)号：US08205182B1
公开(公告)日：2012-06-19
申请号：US12197123
申请日：2008-08-22
申请人： Radu Zlatanovici , Christoph Albrecht , Saurabh Kumar Tiwary
发明人： Radu Zlatanovici , Christoph Albrecht , Saurabh Kumar Tiwary
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F2217/62
摘要： In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.
摘要翻译：在本发明的一个实施例中，公开了一种用于设计集成电路的方法。该方法包括将集成电路设计的时钟信宿自动分为多个分区; 自动将时钟树从主时钟发生器合成到多个分区中，以最小化多个分区内的每个分区内的本地时钟偏移; 并且将时钟去偏移电路自动合成到多个分区中的每一个中以控制相邻分区之间的时钟偏移。

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