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1. 发明授权

US5554562A Advanced isolation scheme for deep submicron technology 失效
公开(公告)号：US5554562A
公开(公告)日：1996-09-10
申请号：US417572
申请日：1995-04-06
申请人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

2. 发明授权

US5821146A Method of fabricating FET or CMOS transistors using MeV implantation 失效
标题翻译：使用MeV植入制造FET或CMOS晶体管的方法
公开(公告)号：US5821146A
公开(公告)日：1998-10-13
申请号：US479880
申请日：1995-06-07
申请人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Fred Hause
发明人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Fred Hause
IPC分类号： H01L21/266 , H01L21/8238 , H01L27/092 , H01L21/336
CPC分类号： H01L21/266 , H01L21/823814 , H01L27/0925
摘要： A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.
摘要翻译：一种制造具有LDD区域的方法，其中通过以1MeV和更大的能量注入离子通过光致抗蚀剂层形成源极和漏极区域，并且在除去氧化物层之后通过低能离子注入形成LDD区域从有源区和门。在第二实施例中，源极和漏极区域通过离子注入形成为没有光致抗蚀剂层，并且在从有源区域和栅极去除氧化物层之后，通过低能离子注入形成LDD区域。

3. 发明授权

US5610088A Method of fabricating field effect transistors having lightly doped drain regions 失效
标题翻译：制造具有轻掺杂漏极区域的场效应晶体管的方法
公开(公告)号：US5610088A
公开(公告)日：1997-03-11
申请号：US405321
申请日：1995-03-16
申请人： Kuang-Yeh Chang , Yowjuang W. Liu
发明人： Kuang-Yeh Chang , Yowjuang W. Liu
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y02P80/30
摘要： A method of fabricating an FET or CMOS transistor that includes lightly doped drain ("LDD") regions which minimizes oxide loss while requiring a lesser number of masks. Consequently, manufacturing cost, cycle times and yield loss can be minimized. In one aspect, the present invention provides a method of fabricating an FET having a LDD region using only one mask, comprising the sequential steps of (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a barrier material layer over said substrate including said gate; (d) forming an oxide layer over said barrier material layer; (e) selectively etching said oxide layer with respect to said barrier material layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.
摘要翻译：一种制造FET或CMOS晶体管的方法，其包括轻掺杂漏极（“LDD”）区域，其最小化氧化物损耗，同时需要较少数量的掩模。因此，制造成本，循环时间和产量损失可以最小化。一方面，本发明提供了一种使用仅一个掩模制造具有LDD区域的FET的方法，包括以下顺序步骤：（a）提供具有由场氧化物区域限定的有源区的衬底; （b）提供具有侧边缘的覆盖所述有源区的一部分的栅极; （c）在包括所述栅极的所述衬底上形成阻挡材料层; （d）在所述阻挡材料层上形成氧化物层; （e）相对于所述阻挡材料层选择性地蚀刻所述氧化物层，以围绕所述栅极的侧边缘形成氧化物侧壁; （f）使用所述氧化物侧壁间隔物作为掩模，在所述栅极的侧边缘周围注入重掺杂的源极和漏极区域; （g）去除所述氧化物侧壁间隔物; 以及（h）在所述重掺杂漏极区附近围绕所述栅极的一个侧边缘注入轻掺杂漏极区。

4. 发明授权

US5904512A Method of making SRAM cell having single layer polysilicon thin film transistors 失效
标题翻译：制造具有单层多晶硅薄膜晶体管的SRAM单元的方法
公开(公告)号：US5904512A
公开(公告)日：1999-05-18
申请号：US895364
申请日：1997-07-16
申请人： Kuang-Yeh Chang , Yowjuang W. Liu
发明人： Kuang-Yeh Chang , Yowjuang W. Liu
IPC分类号： H01L21/768 , H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/76895 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , Y10S257/903
摘要： A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors. This arrangement results in a TFT SRAM cell that can be implemented using simple fabrication techniques, such as single poly logic processes or ASIC processes.
摘要翻译：具有由单个多晶硅层形成的NMOS和薄膜晶体管（TFT）的静态金属氧化物半导体随机存取存储器（SRAM）及其形成方法。 SRAM单元包括通过局部互连结构互连的多个NMOS晶体管和TFT。单层多晶硅用于限定SRAM单元中NMOS晶体管的TFT体和栅极。每个TFT包括包含源极栅极和漏极区域的单个多晶硅层。在制造过程中，TFT多晶硅体的暴露部分和NMOS晶体管的暴露区域分别与难熔金属硅化物反应形成多晶硅化物和硅化物区域。非晶硅图案也与难熔金属硅化物反应形成连接薄膜晶体管和MOS晶体管的硅化部分的局部互连结构。这种布置导致可以使用诸如单个多逻辑处理或ASIC处理之类的简单制造技术来实现的TFT SRAM单元。

5. 发明授权

US5874328A Reverse CMOS method for dual isolation semiconductor device 失效
标题翻译：双隔离半导体器件的反向CMOS方法
公开(公告)号：US5874328A
公开(公告)日：1999-02-23
申请号：US886131
申请日：1997-06-30
申请人： Yowjuang W. Liu , Kuang-yeh Chang
发明人： Yowjuang W. Liu , Kuang-yeh Chang
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/08
CPC分类号： H01L21/823878 , H01L21/76237
摘要： CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.
摘要翻译： CMOS晶体管通过镶嵌工艺形成，导致基本上不显示鸟喙部分的场氧化物区域。在源极/漏极区域中也形成沟槽隔离，每个晶体管在相邻的接合点之间。

6. 发明授权

US5734179A SRAM cell having single layer polysilicon thin film transistors 失效
标题翻译：具有单层多晶硅薄膜晶体管的SRAM单元
公开(公告)号：US5734179A
公开(公告)日：1998-03-31
申请号：US570881
申请日：1995-12-12
申请人： Kuang-Yeh Chang , Yowjuang W. Liu
发明人： Kuang-Yeh Chang , Yowjuang W. Liu
IPC分类号： H01L21/768 , H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/76 , H01L29/94
CPC分类号： H01L21/76895 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , Y10S257/903
摘要： A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors. This arrangement results in a TFT SRAM cell that can be implemented using simple fabrication techniques, such as single poly logic processes or ASIC processes.
摘要翻译：具有由单个多晶硅层形成的NMOS和薄膜晶体管（TFT）的静态金属氧化物半导体随机存取存储器（SRAM）及其形成方法。 SRAM单元包括通过局部互连结构互连的多个NMOS晶体管和TFT。单层多晶硅用于限定SRAM单元中NMOS晶体管的TFT体和栅极。每个TFT包括包含源极栅极和漏极区域的单个多晶硅层。在制造过程中，TFT多晶硅体的暴露部分和NMOS晶体管的暴露区域分别与难熔金属硅化物反应形成多晶硅化物和硅化物区域。非晶硅图案也与难熔金属硅化物反应形成连接薄膜晶体管和MOS晶体管的硅化部分的局部互连结构。这种布置导致可以使用诸如单个多逻辑处理或ASIC处理之类的简单制造技术来实现的TFT SRAM单元。

7. 发明授权

US5693568A Reverse damascene via structures 失效
标题翻译：通过结构反向镶嵌
公开(公告)号：US5693568A
公开(公告)日：1997-12-02
申请号：US572317
申请日：1995-12-14
申请人： Yowjuang W. Liu , Kuang-Yeh Chang
发明人： Yowjuang W. Liu , Kuang-Yeh Chang
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76885
摘要： A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.
摘要翻译：通过沉积第一和第二导电层，蚀刻以在第一导电层中形成导电图案并进行蚀刻以形成包括第二导电层的一部分的互连来形成可靠的互连图案。有利地，避免了需要在电介质层中形成开口并且填充阻挡材料和插塞以及其伴随的缺点。所得到的半导体器件表现出改进的可靠性，更高的操作速度和更好的信噪比。

8. 发明授权

US5608253A Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits 失效
标题翻译：先进的晶体管结构，具有高密度/高性能集成电路的最佳短沟道控制
公开(公告)号：US5608253A
公开(公告)日：1997-03-04
申请号：US408613
申请日：1995-03-22
申请人： Yowjuang W. Liu , Kuang-Yeh Chang
发明人： Yowjuang W. Liu , Kuang-Yeh Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7832 , H01L21/823807 , H01L27/0928 , H01L29/1075 , H01L29/1087 , H01L29/6659 , Y10S257/901
摘要： A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
摘要翻译：通过改善短沟道控制来提高器件缩放的新型MOS晶体管结构包括在MOS晶体管的沟道区下面的掩埋后栅极。与通过电气传递到掩埋后门的阱的单独接触改善了短通道控制而没有性能下降。在优选实施例中，当关闭n沟道MOS晶体管时，背栅极接地。在替代实施例中，掩埋层产生逆行p阱。在一些应用中，可以使用多个掩埋层，其中一个或多个是平面的。 CMOS器件可能具有独立的多重埋后栅。

9. 发明授权

US5877049A Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits 失效
标题翻译：用于形成具有用于高密度/高性能集成电路的最佳短通道控制的先进晶体管结构的方法
公开(公告)号：US5877049A
公开(公告)日：1999-03-02
申请号：US717981
申请日：1996-09-23
申请人： Yowjuang W. Liu , Kuang-Yeh Chang
发明人： Yowjuang W. Liu , Kuang-Yeh Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7832 , H01L21/823807 , H01L27/0928 , H01L29/1075 , H01L29/1087 , H01L29/6659 , Y10S257/901
摘要： A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.
摘要翻译：通过改善短沟道控制来提高器件缩放的新型MOS晶体管结构包括在MOS晶体管的沟道区下面的掩埋后栅极。与通过电气传递到掩埋后门的阱的单独接触改善了短通道控制而没有性能下降。在优选实施例中，当关闭n沟道MOS晶体管时，背栅极接地。在替代实施例中，掩埋层产生逆行p阱。在一些应用中，可以使用多个掩埋层，其中一个或多个是平面的。 CMOS器件可能具有独立的多重埋后栅。

10. 发明授权

US06300180B1 Method for forming an integrated circuit having improved polysilicon resistor structures 失效
标题翻译：用于形成具有改进的多晶硅电阻器结构的集成电路的方法
公开(公告)号：US06300180B1
公开(公告)日：2001-10-09
申请号：US09024475
申请日：1998-02-17
申请人： Kuang-Yeh Chang , Yowjuang W. Liu
发明人： Kuang-Yeh Chang , Yowjuang W. Liu
IPC分类号： H01L218244
CPC分类号： H01L27/11 , H01L27/1112
摘要： A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.
摘要翻译：金属氧化物半导体静态随机存取存储器（SRAM）包括NMOS晶体管和不具有多个多晶硅层的电阻结构。根据第一实施例，SRAM单元包括多个适当互连的NMOS晶体管，其具有由多晶硅层形成的晶体管栅极和由相同多晶硅层形成的电阻器。根据第二实施例，SRAM单元包括多个适当互连的NMOS晶体管，覆盖在NMOS晶体管上的电介质层，以及穿过电介质层的多晶硅电阻，以将NMOS晶体管连接到第一金属层。沉积在NMOS晶体管上的电介质层限定了暴露在NMOS晶体管中的漏极区域的孔。在电介质层上沉积多晶硅层以填充孔，并且去除多余的多晶硅。

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