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1. 发明申请

US20120105692A1 ANTI-BLOOMING PIXEL SENSOR CELL WITH ACTIVE NEUTRAL DENSITY FILTER, METHODS OF MANUFACTURE, AND DESIGN STRUCTURE 有权
标题翻译：具有主动中性密度滤光片的防透镜像素传感器单元，制造方法和设计结构
公开(公告)号：US20120105692A1
公开(公告)日：2012-05-03
申请号：US12915888
申请日：2010-10-29
申请人： Kristin M. ACKERSON , Jeffrey P. GAMBINO , Mark D. JAFFE , Robert K. LEIDY , Richard J. RASSEL , Robert M. RASSEL
发明人： Kristin M. ACKERSON , Jeffrey P. GAMBINO , Mark D. JAFFE , Robert K. LEIDY , Richard J. RASSEL , Robert M. RASSEL
IPC分类号： H04N5/335 , G06F9/45 , H01L31/18
CPC分类号： H04N5/238 , H01L27/14623 , H01L27/14625 , H01L27/14685 , H04N5/3591
摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
摘要翻译：防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

2. 发明申请

US20100171148A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20100171148A1
公开(公告)日：2010-07-08
申请号：US12725792
申请日：2010-03-17
申请人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
发明人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
IPC分类号： H01L27/06
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N− well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N− well, a P+ diffusion region in contact with the N− well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电极的连通结构和形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区和N +和P +扩散区之间的浅沟槽隔离结构。

3. 发明申请

US20120061801A1 STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING A STRUCTURE HAVING VIAS AND HIGH DENSITY CAPACITORS 有权
标题翻译：结构，设计结构和制造VIAS和高密度电容器结构的方法
公开(公告)号：US20120061801A1
公开(公告)日：2012-03-15
申请号：US13302168
申请日：2011-11-22
申请人： David S. COLLINS , Kai D. FENG , Zhong-Xiang HE , Peter J. LINDGREN , Robert M. RASSEL
发明人： David S. COLLINS , Kai D. FENG , Zhong-Xiang HE , Peter J. LINDGREN , Robert M. RASSEL
IPC分类号： H01L29/92
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

4. 发明申请

US20110143494A1 SCHOTTKY BARRIER DIODES FOR MILLIMETER WAVE SiGe BICMOS APPLICATIONS 有权
标题翻译：肖特基二极管适用于千兆波SiGe BICMOS应用
公开(公告)号：US20110143494A1
公开(公告)日：2011-06-16
申请号：US13028673
申请日：2011-02-16
申请人： Jeffrey B. JOHNSON , Xuefeng LIU , Bradley A. ORNER , Robert M. RASSEL
发明人： Jeffrey B. JOHNSON , Xuefeng LIU , Bradley A. ORNER , Robert M. RASSEL
IPC分类号： H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译：一种在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

5. 发明申请

US20120192139A1 INTEGRATED STRUCTURES OF HIGH PERFORMANCE ACTIVE DEVICES AND PASSIVE DEVICES 有权
标题翻译：高性能有源器件和被动器件的集成结构
公开(公告)号：US20120192139A1
公开(公告)日：2012-07-26
申请号：US13426835
申请日：2012-03-22
申请人： Robert M. RASSEL , Anthony K. STAMPER , Daniel S. VANSLETTE
发明人： Robert M. RASSEL , Anthony K. STAMPER , Daniel S. VANSLETTE
IPC分类号： G06F17/50
CPC分类号： H01L25/16 , H01L23/147 , H01L23/49827 , H01L23/50 , H01L23/552 , H01L23/645 , H01L24/13 , H01L24/16 , H01L2223/6661 , H01L2223/6672 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2924/14 , H01L2924/1433 , H01L2924/157 , H01L2924/19011 , H01L2924/19042 , H01L2924/19103 , H01L2924/19107 , H01L2224/48091 , H01L2924/00014
摘要： Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.
摘要翻译：提供了具有安装在无源器件上的高性能CMOS有源器件的集成结构。该结构包括集成无源器件芯片，其具有安装到接地平面的多个通过晶片通孔。该结构还包括使用倒装芯片技术安装在集成无源器件芯片上的至少一个CMOS器件，并通过集成无源器件芯片的贯穿晶片通孔接地到接地层。

6. 发明申请

US20110227130A1 STRUCTURES AND METHODS OF FORMING SIGE AND SIGEC BURIED LAYER FOR SOI/SIGE TECHNOLOGY 有权
标题翻译：用于SOI / SIGE技术的形成信号和SIGEC覆层的结构和方法
公开(公告)号：US20110227130A1
公开(公告)日：2011-09-22
申请号：US13150440
申请日：2011-06-01
申请人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
发明人： Xuefeng LIU , Robert M. RASSEL , Steven H. VOLDMAN
IPC分类号： H01L29/12 , H01L29/06
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76264 , H01L21/823807 , H01L21/8249 , H01L27/0635 , H01L27/0652 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
摘要翻译：半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。器件与Si和SiGe或SiGeC区域相关联。

7. 发明申请

US20120214280A1 HEAT SINK FOR INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：集成电路设备的散热
公开(公告)号：US20120214280A1
公开(公告)日：2012-08-23
申请号：US13460871
申请日：2012-05-01
申请人： Douglas D. COOLBAUGH , Ebenezer E. ESHUN , Terence B. HOOK , Robert M. RASSEL , Edmund J. SPROGIS , Anthony K. STAMPER , William J. MURPHY
发明人： Douglas D. COOLBAUGH , Ebenezer E. ESHUN , Terence B. HOOK , Robert M. RASSEL , Edmund J. SPROGIS , Anthony K. STAMPER , William J. MURPHY
IPC分类号： H01L21/50
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

8. 发明申请

US20120184081A1 PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
标题翻译：单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺
公开(公告)号：US20120184081A1
公开(公告)日：2012-07-19
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. CHINTHAKINDI , Douglas D. COOLBAUGH , Keith E. DOWNES , Ebenezer E. ESHUN , Zhong-Xiang HE , Robert M. RASSEL , Anthony K. STAMPER
发明人： Anil K. CHINTHAKINDI , Douglas D. COOLBAUGH , Keith E. DOWNES , Ebenezer E. ESHUN , Zhong-Xiang HE , Robert M. RASSEL , Anthony K. STAMPER
IPC分类号： H01L21/02
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

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