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1. 发明授权

US08929501B2 Method and apparatus for synchronization of data and error samples in a communications system 有权
标题翻译：用于在通信系统中同步数据和错误样本的方法和装置
公开(公告)号：US08929501B2
公开(公告)日：2015-01-06
申请号：US13482686
申请日：2012-05-29
申请人： Krishnaraj Varma , Tony Huang , Sri Bhat
发明人： Krishnaraj Varma , Tony Huang , Sri Bhat
IPC分类号： H04L7/00
CPC分类号： H04L27/0014 , H04L25/03038 , H04L27/2656 , H04L27/2657 , H04L27/2689 , H04L2025/03477 , H04L2025/03636 , H04L2027/0038
摘要： A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.
摘要翻译：一种用于处理以连续模式或突发模式发送的信号传输的输入数据信号的方法和装置，例如在卫星或计算机网络通信系统中。接收器接收输入数据信号，缓冲器存储所接收的输入数据。处理电路产生用于写入用于存储的输入数据的帧的帧定时同步控制信号，产生与输入数据的处理延迟相对应的定时误差控制信号，用于基于来自缓冲器的存储数据，定时误差控制信号和帧定时同步控制信号在处理输入数据时调整任意延迟。处理电路可以包括用于基于由处理电路产生的均衡器误差信号来产生对应于读出数据的抽头梯度的抽头梯度更新电路。

2. 发明申请

US20130322511A1 METHOD AND APPARATUS FOR SYNCHRONIZATION OF DATA AND ERROR SAMPLES IN A COMMUNICATIONS SYSTEM 有权
标题翻译：用于在通信系统中同步数据和错误样本的方法和装置
公开(公告)号：US20130322511A1
公开(公告)日：2013-12-05
申请号：US13482686
申请日：2012-05-29
申请人： Krishnaraj Varma , Tony Huang , Sri Bhat
发明人： Krishnaraj Varma , Tony Huang , Sri Bhat
IPC分类号： H04L7/00 , H04L27/01 , H04L27/06 , H03H7/40
CPC分类号： H04L27/0014 , H04L25/03038 , H04L27/2656 , H04L27/2657 , H04L27/2689 , H04L2025/03477 , H04L2025/03636 , H04L2027/0038
摘要： A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.
摘要翻译：一种用于处理以连续模式或突发模式发送的信号传输的输入数据信号的方法和装置，例如在卫星或计算机网络通信系统中。接收器接收输入数据信号，缓冲器存储所接收的输入数据。处理电路产生用于写入用于存储的输入数据的帧的帧定时同步控制信号，产生与输入数据的处理延迟相对应的定时误差控制信号，用于基于来自缓冲器的存储数据，定时误差控制信号和帧定时同步控制信号在处理输入数据时调整任意延迟。处理电路可以包括用于基于由处理电路产生的均衡器误差信号来产生对应于读出数据的抽头梯度的抽头梯度更新电路。

3. 发明授权

US10819469B2 High speed interleaver/deinterleaver device supporting line rate, and method thereof 有权
公开(公告)号：US10819469B2
公开(公告)日：2020-10-27
申请号：US16577624
申请日：2019-09-20
申请人： Sri Bhat , Bala Subramaniam , Yanlai Liu
发明人： Sri Bhat , Bala Subramaniam , Yanlai Liu
IPC分类号： H04L1/00 , G06F12/06 , G11C7/10 , G11C7/18 , H03M13/27 , H03M13/00 , H04L27/20 , H03M13/29
摘要： A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.

4. 发明授权

US10484136B2 High speed interleaver/deinterleaver device supporting line rate, and method thereof 有权
公开(公告)号：US10484136B2
公开(公告)日：2019-11-19
申请号：US15615358
申请日：2017-06-06
申请人： Sri Bhat , Bala Subramaniam , Yanlai Liu
发明人： Sri Bhat , Bala Subramaniam , Yanlai Liu
IPC分类号： H04L1/00 , G06F12/06 , G11C7/10 , G11C7/18 , H04L27/20
摘要： A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are provided. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.

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