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1. 发明授权

US07910757B2 Process for the preparation of fatty acids 有权
标题翻译：脂肪酸的制备方法
公开(公告)号：US07910757B2
公开(公告)日：2011-03-22
申请号：US11883642
申请日：2006-02-02
申请人： Krishnadath Bhaggan , Genwang Zhang , Zheng Guo , Shuhong Cheng , Youchun Yan , Erik Schweitzer
发明人： Krishnadath Bhaggan , Genwang Zhang , Zheng Guo , Shuhong Cheng , Youchun Yan , Erik Schweitzer
IPC分类号： C07B35/08
CPC分类号： A61K31/201 , A23L33/12 , A23V2002/00 , C11C3/14 , A23V2250/1866 , A23V2250/1882 , A23V2250/186
摘要： A process for the preparation of a material comprising conjugated isomers of a polyunsaturated fatty acid comprises: treating a first fatty acid mixture comprising saturated fatty acids, monounsaturated fatty acids and polyunsaturated fatty acids in the presence of ethanol to form (i) a solid fraction and (ii) a liquid fraction comprising a second fatty acid mixture, wherein the second fatty acid mixture has a higher molar ratio of total polyunsaturated fatty acids to total saturated and monounsaturated fatty acids than the first fatty acid mixture; separating the solid fraction and the liquid fraction; and subjecting the second fatty acid mixture or a derivative or reaction product thereof to treatment with a base in the presence of a solvent, to form conjugated isomers of at least some of the polyunsaturated fatty acids.
摘要翻译：一种制备包含多不饱和脂肪酸的共轭异构体的材料的方法包括：在乙醇存在下，将包含饱和脂肪酸，单不饱和脂肪酸和多不饱和脂肪酸的第一脂肪酸混合物处理，以形成（i）固体部分和（ii）包含第二脂肪酸混合物的液体级分，其中所述第二脂肪酸混合物具有比所述第一脂肪酸混合物更高的总多不饱和脂肪酸与总饱和和单不饱和脂肪酸的摩尔比; 分离固体部分和液体部分; 并在溶剂存在下，用碱处理第二脂肪酸混合物或其衍生物或反应产物，以形成至少一些多不饱和脂肪酸的共轭异构体。

2. 发明授权

US07693926B2 Modular multiplication acceleration circuit and method for data encryption/decryption 失效
标题翻译：模块化乘法加速电路和数据加密/解密方法
公开(公告)号：US07693926B2
公开(公告)日：2010-04-06
申请号：US11393392
申请日：2006-03-30
申请人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
发明人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F7/722
摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.
摘要翻译：处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M，的X和位2w-1：w，以产生乘积Z的位2w-1：w，并将模数M的位2w-1：w加到乘积Z的位2w-1：w，如果最不重要乘积Z为1.乘以X的最低有效位和Y的位2w-1：w可以至少部分同时与X的最低有效位和Y的最低有效位相乘，从而确定如果乘积Z的最低有效位为1，并将模数M的最低有效位W加到最小值如果产品Z的最低有效位为1，则不能产生Z位。

3. 发明申请

US20070183185A1 FINFET-BASED SRAM WITH FEEDBACK 审中-公开
标题翻译：具有反馈功能的基于FINFET的SRAM
公开(公告)号：US20070183185A1
公开(公告)日：2007-08-09
申请号：US11622305
申请日：2007-01-11
申请人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
发明人： Zheng Guo , Sriram Balasubramanian , Radu Zlatanovici , Tsu-Jae King , Borivoje Nikolic
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/785
摘要： Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.
摘要翻译：当前体硅Si MOSFET中的固有变化和具有挑战性的泄漏控制迫使不需要的折衷，并限制了SRAM电路的缩放。本文教导了改善SRAM单元中的泄漏和噪声容限的电路和机构，例如包括六晶体管（6-T）SRAM单元设计或四晶体管（4-T）SRAM单元设计）的那些。本发明的SRAM单元利用将存储节点的一部分耦合到存取晶体管的后栅极的反馈装置。反馈优选以这种方式耦合到两个存取晶体管。使用这种内置反馈设计的SRAM单元实现了细胞静态噪声容限（SNM）的显着改进，无区域损失。反馈方案的使用还导致创建了实用的基于4-T FinFET的SRAM单元，其实现了每个100pA的每个电池的待机电流，并且具有与具有反馈的6-T电池相似的SNM改进。

4. 发明申请

US20070233772A1 Modular multiplication acceleration circuit and method for data encryption/decryption 失效
标题翻译：模块化乘法加速电路和数据加密/解密方法
公开(公告)号：US20070233772A1
公开(公告)日：2007-10-04
申请号：US11393392
申请日：2006-03-30
申请人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
发明人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
IPC分类号： G06F7/52
CPC分类号： G06F7/728 , G06F7/722
摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.
摘要翻译：处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M，并且产生Z的位2 w-1：w，并将模数M的位2 w-1：w相加到乘积Z的位2 w-1：w，如果乘积Z的最低有效位为1.乘以X的最低有效位和Y的位2 w-1：w可以至少部分同时与X的最低有效位乘以最小有效位W 确定产品Z的最低有效位是否为1，并将模数M的最低有效W位加到第如果产品Z的最低有效位为1，则产品Z的最低有效w位。

5. 发明申请

US20190351273A1 Horizontal Bar Device 审中-公开
公开(公告)号：US20190351273A1
公开(公告)日：2019-11-21
申请号：US16244123
申请日：2019-01-10
申请人： Caihua Shan , Zheng Guo , Gaoyang Xu , Ruzhong Yin , Rixin Liang , Ying Fan
发明人： Caihua Shan , Zheng Guo , Gaoyang Xu , Ruzhong Yin , Rixin Liang , Ying Fan
IPC分类号： A63B1/00
摘要： A horizontal bar device comprises at least three vertically disposed struts, and crossbars connected between the two adjacent struts. A plurality of sleeves are sleeved on an upper part of each of the struts with the sleeves being stacked on top of one another, each end of each of the crossbars is fixedly connected to one of the sleeves, and each of the struts has a blocking surface capable of preventing the sleeves from sliding downward. A positioning structure is disposed between the two adjacent sleeves capable of preventing rotation of the sleeves. An upper end of each of the struts is sleeved with a locking sleeve, and the locking sleeve is pressed against the sleeves through a fastener.

6. 发明申请

US20140269019A1 DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) 有权
标题翻译：双端口静态随机存取存储器（SRAM）
公开(公告)号：US20140269019A1
公开(公告)日：2014-09-18
申请号：US13842086
申请日：2013-03-15
申请人： Pramod Kolar , Gunjan H. Pandya , Uddalak Bhattacharya , Zheng Guo
发明人： Pramod Kolar , Gunjan H. Pandya , Uddalak Bhattacharya , Zheng Guo
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412
摘要： In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.
摘要翻译：在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。接入设备提供对一对交叉耦合逆变器的访问。存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

7. 发明申请

US20070233760A1 3:2 Bit compressor circuit and method 审中-公开
标题翻译： 3：2位压缩机电路及方法
公开(公告)号：US20070233760A1
公开(公告)日：2007-10-04
申请号：US11392070
申请日：2006-03-29
申请人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
发明人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F7/501 , G06F7/5016
摘要： A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and the second block may receive the three bits and output a carry bit.
摘要翻译：将三个输入位（A，B和C）转换为冗余格式的电路可以包括具有至少一个传输门的第一块和具有至少一个静态镜的第二块。第一块可以接收三位并输出和位，第二块可以接收三位并输出进位位。

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