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1. 发明授权

US07174346B1 System and method for searching an extended database 有权
标题翻译：用于搜索扩展数据库的系统和方法
公开(公告)号：US07174346B1
公开(公告)日：2007-02-06
申请号：US10676650
申请日：2003-09-30
申请人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach , Sanjay Ghemawat , Jeffrey Dean
发明人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach , Sanjay Ghemawat , Jeffrey Dean
IPC分类号： G06F17/30
CPC分类号： G06F17/30864 , G06F17/30619 , Y10S707/99942 , Y10S707/99943 , Y10S707/99944 , Y10S707/99945
摘要： Once a search query is received from a user, a standard index is searched based on the search query. The standard index forms part of a set of replicated standard indexes having multiple instances of the standard index. A signal is then determined based on the search of the standard index. When the received signal meets predefined criteria, an extended index is searched. The extended index forms part of a set of extended indexes having at least one instance of the extended index. There are fewer instances of the extended index than instances of the standard index. Extended search results are then obtained from the extended index and at least a portion of the extended search results is transmitted towards a user.
摘要翻译：一旦从用户接收到搜索查询，就会根据搜索查询来搜索标准索引。标准索引构成了具有标准索引的多个实例的一组复制标准索引的一部分。然后基于标准索引的搜索来确定信号。当接收到的信号满足预定标准时，搜索扩展索引。扩展索引构成一组具有扩展索引的至少一个实例的扩展索引的一部分。扩展索引的实例少于标准索引的实例。然后从扩展索引获得扩展搜索结果，并向用户发送扩展搜索结果的至少一部分。

2. 发明授权

US07254580B1 System and method for selectively searching partitions of a database 有权
标题翻译：用于选择性地搜索数据库分区的系统和方法
公开(公告)号：US07254580B1
公开(公告)日：2007-08-07
申请号：US10676651
申请日：2003-09-30
申请人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach , Sanjay Ghemawat , Jeffrey Dean
发明人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach , Sanjay Ghemawat , Jeffrey Dean
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30545 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： When a search query is received, a plurality of partition indexes are searched using the set of search terms in the search query. Each partition index corresponds to a partition of a document index. The search of each respective partition index identifies a subset of a plurality of document index sub-partitions corresponding to the respective partition index. Next, the search query is executed by only those document index sub-partitions identified by the subsets, thereby identifying documents that satisfy the search query. By using the partition index to reduce the number of document index sub-partitions searched while executing a search query, the execution of the search query is made more efficient.
摘要翻译：当接收到搜索查询时，使用搜索查询中的搜索项集来搜索多个分区索引。每个分区索引对应于文档索引的分区。每个相应分区索引的搜索标识对应于相应分区索引的多个文档索引子分区的子集。接下来，搜索查询仅由由子集标识的那些文档索引子分区执行，从而识别满足搜索查询的文档。通过使用分区索引来减少在执行搜索查询时搜索的文档索引子分区的数量，使得搜索查询的执行更有效。

3. 发明授权

US07467131B1 Method and system for query data caching and optimization in a search engine system 有权
标题翻译：在搜索引擎系统中查询数据缓存和优化的方法和系统
公开(公告)号：US07467131B1
公开(公告)日：2008-12-16
申请号：US10676646
申请日：2003-09-30
申请人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach
发明人： Kourosh Gharachorloo , Fay Wen Chang , Deborah Anne Wallach
IPC分类号： G06F7/00 , G06F12/00 , G06F15/16 , G06F17/00
CPC分类号： G06F17/30902 , Y10S707/99933 , Y10S707/99945
摘要： When searching a document database in response to a search query, a determination is made as to whether a query result corresponding to the search query is stored in a cache. When the query result is stored in the cache, a reuse count for the search query is accessed. When predefined conditions are satisfied, such as the reuse count being larger than a predetermined threshold count, an improved search result is generated in accordance with a first set of predetermined searching criteria, and at least a subset of the improved search result is returned.
摘要翻译：响应于搜索查询搜索文档数据库时，确定与搜索查询相对应的查询结果是否存储在高速缓存中。当查询结果存储在缓存中时，可以访问搜索查询的重用计数。当满足预定义条件（诸如重用计数大于预定阈值计数）时，根据第一组预定搜索条件生成改进的搜索结果，并且返回改进的搜索结果的至少一个子集。

4. 发明授权

US06988170B2 Scalable architecture based on single-chip multiprocessing 有权
标题翻译：基于单芯片多处理的可扩展架构
公开(公告)号：US06988170B2
公开(公告)日：2006-01-17
申请号：US10693388
申请日：2003-10-24
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0826 , G06F2212/621
摘要： A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRAHNA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.
摘要翻译：具有可扩展架构的芯片多处理系统，包括在单个芯片上：多个处理器内核; 两级缓存层次结构; 片内开关; 一个或多个存储器控制器; 缓存一致性协议; 一个或多个一致性协议引擎; 和互连子系统。两级缓存层次结构包括第一级和第二级缓存。特别地，第一级高速缓存包括用于每个处理器核的私有指令和数据高速缓存。第二级缓存具有轻松的包含属性，第二级缓存由多个处理器核逻辑地共享。多个处理器核心中的每一个能够执行ALPHA TM处理核心的指令集。芯片多处理系统的可扩展架构针对并行商业工作负载。称为PIRAHNA（TM）系统的芯片多处理系统的展示示例是具有八个更简单的ALPHA（TM）处理器内核的高度集成的处理节点。还提供了一种可扩展的芯片多处理方法。

5. 发明授权

US06751710B2 Scalable multiprocessor system and cache coherence method 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法
公开(公告)号：US06751710B2
公开(公告)日：2004-06-15
申请号：US09878982
申请日：2001-06-11
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets, Jr. , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets, Jr. , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
摘要翻译：本发明一般涉及多处理器计算机系统，特别涉及使用有效的高速缓存一致性逻辑和方法来设计为高度可扩展的多处理器系统。更具体地说，本发明是一种包括多个处理器节点的系统和方法，所述多个处理器节点被配置为执行避免使用否定确认消息（NAK）的高速缓存一致性协议以及对底层事务 - 消息互联/网络和服务的排序要求只有一次访问家庭节点的3跳交易。

6. 发明授权

US06678840B1 Fault containment and error recovery in a scalable multiprocessor 有权
标题翻译：可扩展多处理器中的故障控制和错误恢复
公开(公告)号：US06678840B1
公开(公告)日：2004-01-13
申请号：US09651949
申请日：2000-08-31
申请人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
发明人： Richard E. Kessler , Peter J. Bannon , Kourosh Gharachorloo , Thukalan V. Verghese
IPC分类号： G06F1100
CPC分类号： G06F11/0793 , G06F11/0724 , G06F15/17
摘要： A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
摘要翻译：多处理器计算机系统允许实现各种类型的分区以包含和隔离硬件故障。各种类型的分区包括硬，半硬，坚固和软分区。每个分区可以包括一个或多个处理器。当检测到与处理器相关联的故障时，可以切断与系统中的相邻处理器的连接，从而防止损坏的数据污染系统的其余部分。如果处理器间连接被切断，则在其他处理器中的消息备份时，系统中的消息流量可能会变得拥塞。因此，每个处理器包括各种定时器，以监视可能由于切断的连接造成的交通拥堵。而不是让处理器继续等待能够发送其消息，定时器将在预编程的时间段过期，并且处理器将采取适当的动作，例如简单地删除排队的消息，以防止系统锁定。

7. 发明授权

US06622217B2 Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system 失效
标题翻译：缓存一致性协议引擎系统和方法，用于在多处理器系统中的交织时间段期间处理不同地址子集中的存储器事务
公开(公告)号：US06622217B2
公开(公告)日：2003-09-16
申请号：US09878983
申请日：2001-06-11
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J Stets, Jr. , Andreas Nowatzyk
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J Stets, Jr. , Andreas Nowatzyk
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F2212/621
摘要： The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.
摘要翻译：本发明一般涉及在多处理器计算机系统中使用的协议引擎。实现高速缓存一致性协议的协议引擎包括时钟信号发生器，用于产生表示交织的偶数时钟周期和奇数时钟周期的信号，存储事务状态阵列，用于存储条目，每个表示各自的存储器事务的状态，以及处理逻辑。存储器事务被分为偶数和奇数事务，其状态存储在存储器事务状态数组中的不同的条目集合中。处理逻辑具有交织电路，用于在甚至时钟周期期间处理偶数存储器事务并且用于在奇数时钟周期期间处理奇数存储器事务。

8. 发明授权

US5933598A Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures 失效
标题翻译：通过发送包括块的行和大小的特定块来交换共享数据结构来共享工作站的可变粒度存储器的方法
公开(公告)号：US5933598A
公开(公告)日：1999-08-03
申请号：US682348
申请日：1996-07-17
申请人： Daniel J. Scales , Kourosh Gharachorloo
发明人： Daniel J. Scales , Kourosh Gharachorloo
IPC分类号： G06F9/50 , G06F13/00
CPC分类号： G06F9/5016
摘要： In a distributed shared memory system, workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface to interconnect the workstations. A software implemented method enables data sharing between the workstations using variable sized quantities of data. A set of the addresses of the memories are designated as virtual shared addresses to store shared data. A portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The shared data structure is accessible by programs executing in any of the processors. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Access information of a particular block is stored in the memory of a home one of the workstations. The access information includes the size of the particular block and an identity of workstations having a copy of the block.
摘要翻译：在分布式共享存储器系统中，工作站通过网络彼此连接。每个工作站包括处理器，具有地址的存储器以及用于互连工作站的输入/输出接口。软件实现的方法使得可以使用可变大小数据的数据在工作站之间进行数据共享。一组存储器的地址被指定为虚拟共享地址以存储共享数据。虚拟共享地址的一部分被分配以将共享数据结构存储为一个或多个块。共享数据结构可由在任何处理器中执行的程序访问。特定分配的块的大小可以针对不同的共享数据结构而变化。每个块包括整数行，并且每行包括预定数量的共享数据字节。特定块的访问信息被存储在家庭工作站的存储器中。访问信息包括特定块的大小和具有该块的副本的工作站的标识。

9. 发明授权

US07523016B1 Detecting anomalies 有权
标题翻译：检测异常
公开(公告)号：US07523016B1
公开(公告)日：2009-04-21
申请号：US11618607
申请日：2006-12-29
申请人： Razvan Surdulescu , Kourosh Gharachorloo
发明人： Razvan Surdulescu , Kourosh Gharachorloo
IPC分类号： G06F11/30 , G21C17/00
CPC分类号： H04L63/1416 , G06F21/316 , G06F21/552 , G06Q30/00 , H04L63/1425
摘要： In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically derived measures of how extreme the cell is relative to, for example, historical behavior of corresponding characteristics or relative to, for example, behavior of characteristics from a general population. Cells that have more than a predefined number of such annotations can be identified as anomalous and can be investigated by a user or outright acted upon in an automatic, pre-defined way.
摘要翻译：一般来说，描述用于识别异常活动的系统和方法。例如，描述了系统和方法，其中可以通过将记录的或采样的数据聚合到单元中并且通过统计学上导出的测量来注释每个单元来识别该异常行为的模式，该度量对于诸如历史行为或相对于例如来自普通人群的特征的行为。具有超过预定数量的这种注释的单元可以被识别为异常的，并且可以由用户进行调查或直接以自动的，预定义的方式进行操作。

10. 发明授权

US07502895B2 Techniques for reducing castouts in a snoop filter 有权
标题翻译：用于减少窥探过滤器中的铸件的技术
公开(公告)号：US07502895B2
公开(公告)日：2009-03-10
申请号：US11225937
申请日：2005-09-13
申请人： Phillip Matthew Jones , Kourosh Gharachorloo
发明人： Phillip Matthew Jones , Kourosh Gharachorloo
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0831
摘要： Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.
摘要翻译：用于减少窥探过滤器中的铸件的方法和装置。更具体地，提供了一种包括多个总线，耦合到多个总线中的每一个的一个或多个处理器和窥探滤波器的系统。所述窥探过滤器被配置为消除所述多个总线中的不必要的窥探，并且还被配置为仅在跟踪所述请求不导致停顿罚分时才跟踪来自所述一个或多个处理器的请求。

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