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1. 发明授权

US6163183A Multifunction reset for mixed-signal integrated circuits 有权
标题翻译：混合信号集成电路的多功能复位
公开(公告)号：US6163183A
公开(公告)日：2000-12-19
申请号：US356043
申请日：1999-07-16
申请人： Kouros Azimi , Zhigang Ma , Dale H. Nelson , Brian J. Petryna , Oceager P. Yee
发明人： Kouros Azimi , Zhigang Ma , Dale H. Nelson , Brian J. Petryna , Oceager P. Yee
IPC分类号： G01R31/3167 , H03K17/22 , H03L7/00
CPC分类号： G01R31/3167 , H03K17/223
摘要： A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.
摘要翻译：包括低功率带隙，比较器和开漏缓冲电路的多功能复位电路 - 包括四个外部组件（三个电阻器和一个电容器），以提供欠压监控，停电指示，手动复位和其他复位控制条件单个集成电路端子，以及滞后公差。

2. 发明授权

US07315556B1 Shared CODEC in multiprocessor systems 失效
标题翻译：多处理器系统中的共享编解码器
公开(公告)号：US07315556B1
公开(公告)日：2008-01-01
申请号：US09629707
申请日：2000-07-31
申请人： Zhigang Ma , Brian J. Petryna , Oceager P. Yee
发明人： Zhigang Ma , Brian J. Petryna , Oceager P. Yee
IPC分类号： H04J3/02
CPC分类号： H04L12/66
摘要： A single coder/decoder shared among several multiprocessors in a digital signal processing system through time-division multiplexing between multiple processors to enhance signal processing capabilities by assigning different digital-to-analog channels to different processors for digital-to-analog conversion, while allowing all processors to operate on the same analog-to-digital data for analog-to-digital conversion, thereby resulting in chip area reduction and power consumption saving.
摘要翻译：通过在多个处理器之间的时分多路复用在数字信号处理系统中的多个多处理器之间共享的单个编码器/解码器，以通过将不同的数模转换通道分配给不同的处理器进行数模转换来增强信号处理能力，同时允许所有处理器在相同的模拟数字数据上进行模数转换，从而节省了芯片面积和降低功耗。

3. 发明授权

US06496880B1 Shared I/O ports for multi-core designs 有权
标题翻译：用于多核设计的共享I / O端口
公开(公告)号：US06496880B1
公开(公告)日：2002-12-17
申请号：US09383638
申请日：1999-08-26
申请人： Zhigang Ma , Oceager P. Yee
发明人： Zhigang Ma , Oceager P. Yee
IPC分类号： G06F300
CPC分类号： G06F1/22
摘要： The present invention provides a shared I/O port and a configurable interconnect allowing any of a plurality of cores to access any pin of a shared I/O port. Preferably, one of the plurality of cores is designated as a master core at least with respect to the configuration of the shared I/O port(s), and the remaining cores desiring to gain access to the shared I/O port(s) are designated as non-master or slave cores. It is the responsibility of the master core to reassign chip resources such as the shared I/O port(s) for use by either the master core or by any of the shared cores. Preferably, all shared I/O ports are controlled by default by the master core. The slave cores communicate with the master core through a suitable internal messaging system. If a slave core requires use of a particular I/O pin or I/O port not already configured appropriately for its use, the slave core will send an appropriate message to the master core through the messaging system, e.g., a dual port memory mailbox. Preferably, the master core will then pass a message back to the requesting slave core indicating completion of the requested reconfiguration. The master core preferably keeps track of which core currently has control of each I/O pin or port using appropriate internal registers. The master core communicates with the relevant I/O pin or port using its I/O data bus, while the slave core communicates with the relevant I/O pin or port using its I/O data bus. IOP configuration signals from the master core configure and thus determine which core in the multi-core integrated circuit or hybrid circuit has access to I/O control modules or registers to control the direction, mode, interrupt generation capability, and/or status of the shared I/O port(s).
摘要翻译：本发明提供一种共享的I / O端口和可配置的互连，允许多个核心中的任一个访问共享的I / O端口的任何引脚。优选地，至少相对于共享的I / O端口的配置，将多个核心中的一个核心指定为主核心，并且其余核心希望获得对共享的I / O端口的访问，被指定为非主或从核。主核心负责重新分配芯片资源，例如由主内核或任何共享内核使用的共享I / O端口。优选地，所有共享I / O端口由主核心默认地控制。从核心通过适当的内部消息系统与主核心通信。如果从核心需要使用尚未适当配置的特定I / O引脚或I / O端口供其使用，则从核心将通过消息系统向主核发送适当的消息，例如双端口存储信箱。优选地，主核心然后将消息返回给请求的从核，指示所请求的重新配置的完成。主核心优选地使用适当的内部寄存器跟踪哪个核心当前具有对每个I / O引脚或端口的控制。主核使用其I / O数据总线与相关I / O引脚或端口进行通信，而从器件使用其I / O数据总线与相关I / O引脚或端口进行通信。来自主核心的IOP配置信号配置，从而确定多核集成电路或混合电路中的哪个核心可以访问I / O控制模块或寄存器来控制方向，模式，中断产生能力和/或状态共享I / O端口。

4. 发明授权

US06598178B1 Peripheral breakpoint signaler 失效
标题翻译：外设断点信号器
公开(公告)号：US06598178B1
公开(公告)日：2003-07-22
申请号：US09322920
申请日：1999-06-01
申请人： Oceager P. Yee , Zhigang Ma
发明人： Oceager P. Yee , Zhigang Ma
IPC分类号： G06F1130
CPC分类号： G06F11/3632
摘要： The present invention provides an architecture for a peripheral device to activate a breakpoint in a processor or other device under emulation. A peripheral breakpoint active signaler allows the peripheral to signal the occurrence of a breakpoint to the processor using a halt or trap line to the processor. This invention provides developers with increased code development capabilities by allowing them to set breakpoints in a peripheral device for the benefit of a processor interfaced with the peripheral to detect when a certain external event has occurred based on the perspective of a peripheral. A breakpoint control register individually enables breakpointing capability of each peripheral with respect to having the capability to halt the processor. Each peripheral has the capability to output a breakpoint request signal to set a bit in a breakpoint status register for readback by the processor, through an external port such as a JTAG test port, or other device.
摘要翻译：本发明提供了一种用于外围设备在仿真下激活处理器或其他设备中的断点的架构。外设断点有源信号发生器允许外设使用停止或陷阱线向处理器发出断点的发生。本发明通过允许他们在外围设备中设置断点，为开发人员提供增加的代码开发能力，以便与外围设备接口的处理器有利，以便根据外围设备的视角来检测某个外部事件何时发生。断点控制寄存器单独启用每个外设关于具有停止处理器能力的断点能力。每个外围设备都有能力输出断点请求信号，以设置断点状态寄存器中的位，以便处理器通过外部端口（如JTAG测试端口或其他设备）进行回读。

5. 发明授权

US07471123B2 Fractional-N baseband frequency synthesizer in bluetooth applications 有权
标题翻译：分数N基带频率合成器在蓝牙应用
公开(公告)号：US07471123B2
公开(公告)日：2008-12-30
申请号：US11109701
申请日：2005-04-20
申请人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
发明人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
IPC分类号： H03K21/00
CPC分类号： G06F7/68 , H03L7/1976
摘要： A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
摘要翻译：具有在BLUETOOTH微微网器件中特别使用的基带时钟合成器，具有产生从任何参考时钟信号（例如12.00,12.80,13.00,15.36,16.80,19.20,15.46,19.80,19.20,19.44,19.68）产生的12MHz或13MHz时钟信号的能力。，19.80和26.00MHz。分数N分频器由PLL包括可变分频器实现，允许使用实际上任何参考频率输入来产生用作12MHz或13MHz基带时钟信号的基础的锁定的156MHz时钟信号。残留反馈Σ-Δ调制器在PLL的反馈路径中向整数分频器提供变化的整数序列，有效地允许在PLL中除以非整数。因此，PLL可以参考实际上任何参考时钟，并且仍然提供固定的输出时钟信号（例如，12或13MHz）。

6. 发明授权

US06946884B2 Fractional-N baseband frequency synthesizer in bluetooth applications 失效
标题翻译：分数N基带频率合成器在蓝牙应用
公开(公告)号：US06946884B2
公开(公告)日：2005-09-20
申请号：US10131210
申请日：2002-04-25
申请人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
发明人： William Eric Holland , Wenzhe Luo , Zhigang Ma , Dale H. Nelson , Harold Thomas Simmonds , Lizhong Sun , Xiangqun Sun
IPC分类号： H03L7/197 , H03K21/00
CPC分类号： G06F7/68 , H03L7/1976
摘要： A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
摘要翻译：具有在BLUETOOTH微微网器件中特别使用的基带时钟合成器，具有产生从任何参考时钟信号（例如12.00,12.80,13.00,15.36,16.80,19.20,15.46,19.80,19.20,19.44,19.68）产生的12MHz或13MHz时钟信号的能力。，19.80和26.00MHz。分数N分频器由PLL包括可变分频器实现，允许使用实际上任何参考频率输入来产生用作12MHz或13MHz基带时钟信号的基础的锁定的156MHz时钟信号。残留反馈Σ-Δ调制器在PLL的反馈路径中向整数分频器提供变化的整数序列，有效地允许在PLL中除以非整数。因此，PLL可以参考实际上任何参考时钟，并且仍然提供固定的输出时钟信号（例如，12或13MHz）。

7. 发明申请

US20110201384A1 Cordless Telephone with Digital Audio Player Capability 有权
标题翻译：数字音频播放器功能的无绳电话
公开(公告)号：US20110201384A1
公开(公告)日：2011-08-18
申请号：US13096420
申请日：2011-04-28
申请人： Qinghong Cao , Liang Jin , Wenzhe Luo , Jian Wu , Zhigang Ma
发明人： Qinghong Cao , Liang Jin , Wenzhe Luo , Jian Wu , Zhigang Ma
IPC分类号： H04W88/02
CPC分类号： H04M1/72558 , H04M1/57 , H04M1/6041 , H04M1/72502 , H04M1/72527
摘要： A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.
摘要翻译：一种无绳电话，允许用户使用无绳电话的远程手机来播放MP3数字音频比特流音乐，以控制MP3播放器的功能。无绳电话保持可用作典型的无绳电话，具有无绳电话的所有特征和便利性，包括但不限于主叫方和被叫方之间的电话呼叫的连接，呼叫者ID信息，语音消息收发特征等 MP3数字音频比特流音乐可以通过例如因特网和PC从远程源下载。

8. 发明申请

US20060238226A1 Fractional-N baseband frequency synthesizer in bluetooth applications 有权
公开(公告)号：US20060238226A1
公开(公告)日：2006-10-26
申请号：US11109701
申请日：2005-04-20
申请人： William Holland , Wenzhe Luo , Zhigang Ma , Dale Nelson , Harold Simmonds , Lizhong Sun , Xiangqun Sun
发明人： William Holland , Wenzhe Luo , Zhigang Ma , Dale Nelson , Harold Simmonds , Lizhong Sun , Xiangqun Sun
IPC分类号： H03K23/00
CPC分类号： G06F7/68 , H03L7/1976
摘要： A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

9. 发明授权

US06993300B2 Accurate gain direct modulation (KMOD) using a dual-loop PLL 失效
公开(公告)号：US06993300B2
公开(公告)日：2006-01-31
申请号：US10131213
申请日：2002-04-25
申请人： Wenzhe Luo , Zhigang Ma
发明人： Wenzhe Luo , Zhigang Ma
IPC分类号： H04B1/02
CPC分类号： H03C3/0991 , H03C3/0958 , H03L7/0893 , H03L7/099 , H03L7/18 , H03L2207/06
摘要： The present invention provides a baseband RF clock synthesizer having particular use in a BLUETOOTH piconet device, which has the capability of providing simple and accurate calibration of modulation path gain (KMOD) by introducing a dual-loop phase locked loop (PLL) in the RF clock signal synthesizer. The disclosed technique and apparatus controls the maximum frequency deviation by the difference of two locked frequencies, one frequency in each path of the dual-path PLL. Once the PLL is locked within some frequency error, the present technique and apparatus calibrates for the deviation of amplitude of the modulation due to the modulation path. Accordingly, modulation gain (KMOD) calibration is provided by adding an auxiliary loop to a PLL in an RF frequency synthesizer.

10. 发明授权

US06642797B1 Normalization methods for automatic requency compensation in bluetooth applications 失效
标题翻译：蓝牙应用中自动请求补偿的归一化方法
公开(公告)号：US06642797B1
公开(公告)日：2003-11-04
申请号：US10131212
申请日：2002-04-25
申请人： Wenzhe Luo , Zhigang Ma
发明人： Wenzhe Luo , Zhigang Ma
IPC分类号： H03L700
CPC分类号： H03J7/045 , H04L2027/0026
摘要： An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.
摘要翻译：为微微网应用提供了改进的自动频率补偿（AFC）技术和装置，例如BLUETOOTH TM应用。特别地，本发明提供了一种偏移归一化器，其使频偏偏移最大化偏差归一化。通过归一化频率偏移，在确定本地振荡器的调整之前，本地振荡器调整对于沿着接收路径的增益（包括在解调器中）而变得不相关。因此，可以在微微网设备中对本地振荡器进行非常精确的调整，以提供极其精确的自动频率补偿。

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