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1. 发明授权

US08179729B2 Memory circuit and voltage detection circuit including the same 有权
标题翻译：存储电路和电压检测电路包括相同的
公开(公告)号：US08179729B2
公开(公告)日：2012-05-15
申请号：US12847147
申请日：2010-07-30
申请人： Kotaro Watanabe , Tomohiro Oka , Teruo Suzuki
发明人： Kotaro Watanabe , Tomohiro Oka , Teruo Suzuki
IPC分类号： G11C5/14
CPC分类号： G11C5/143
摘要： Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.
摘要翻译：提供具有小电路规模的存储电路和包括存储电路的电压检测电路。 NMOS晶体管（21）在加载和写入期间处于截止状态，并且在读取期间处于导通状态。当接收到高电平输入时，NMOS晶体管（22）导通，当接收到低电平输入时，NMOS晶体管截止。 NMOS晶体管（23）在加载和写入期间处于截止状态，并且在读取期间处于导通状态。 PMOS晶体管（26）在加载期间处于导通状态，并且在写入和读取期间处于关闭状态。当加载期间接收到高电平输入时，PMOS晶体管（27）截止，在加载期间接收到低电平输入时导通，并且在写入和读取期间处于导通状态。

2. 发明申请

US20110032776A1 MEMORY CIRCUIT AND VOLTAGE DETECTION CIRCUIT INCLUDING THE SAME 有权
标题翻译：存储器电路和电压检测电路，包括它们
公开(公告)号：US20110032776A1
公开(公告)日：2011-02-10
申请号：US12847147
申请日：2010-07-30
申请人： Kotaro Watanabe , Tomohiro Oka , Teruo Suzuki
发明人： Kotaro Watanabe , Tomohiro Oka , Teruo Suzuki
IPC分类号： G11C5/14
CPC分类号： G11C5/143
摘要： Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.
摘要翻译：提供具有小电路规模的存储电路和包括存储电路的电压检测电路。 NMOS晶体管（21）在加载和写入期间处于截止状态，并且在读取期间处于导通状态。当接收到高电平输入时，NMOS晶体管（22）导通，当接收到低电平输入时，NMOS晶体管截止。 NMOS晶体管（23）在加载和写入期间处于截止状态，并且在读取期间处于导通状态。 PMOS晶体管（26）在加载期间处于导通状态，并且在写入和读取期间处于关闭状态。当加载期间接收到高电平输入时，PMOS晶体管（27）截止，在加载期间接收到低电平输入时导通，并且在写入和读取期间处于导通状态。

3. 发明授权

US07835188B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07835188B2
公开(公告)日：2010-11-16
申请号：US12361620
申请日：2009-01-29
申请人： Yutaka Satou , Fumiyasu Utsunomiya , Tomohiro Oka
发明人： Yutaka Satou , Fumiyasu Utsunomiya , Tomohiro Oka
IPC分类号： G11C16/00
CPC分类号： G11C29/50 , G11C16/04 , G11C29/50004
摘要： Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltage portion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal and a voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; a comparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode.
摘要翻译：提供一种半导体存储器件，即使在通过与正电位的情况相似的测试方法的阈值电压为负电位的情况下也实现特性评估。半导体存储器件包括用于存储数据的多个存储单元。当输入测试信号时，半导体存储器件从正常模式改变为用于评估多个存储器单元的特性的测试模式。半导体存储装置还包括：存储单元选择部，用于选择存储单元; 用于产生参考电压的恒定电压部分; 用于产生参考电流的恒定电流部分; X开关电压切换控制电路，用于将X选择信号和从外部端子输入的电压信号中的一个提供给存储器单元的栅极; Y开关部分，用于将参考电流提供给由Y选择信号选择的存储器单元的漏极; 用于检测作为所述漏极的电压的漏极电压是否超过所述参考电压的比较器; 以及判定电平改变部分，用于调整参考电流的当前值和参考电压的电压值，以便基于测试模式中的控制信号来改变比较器的判定电平。

4. 发明授权

US07911259B2 Voltage switching circuit 有权
标题翻译：电压开关电路
公开(公告)号：US07911259B2
公开(公告)日：2011-03-22
申请号：US12513976
申请日：2007-11-07
申请人： Tomohiro Oka
发明人： Tomohiro Oka
IPC分类号： H03K17/693 , H01L27/088 , G11C5/14
CPC分类号： H03K19/018521 , H03K19/0013 , H03K19/0016 , H03K2217/0018 , Y10T307/724 , Y10T307/858
摘要： A voltage switching circuit selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes a first PMOS transistor that outputs a power supply voltage for operating a logic circuit of an output terminal. A second PMOS transistor outputs a first voltage higher than the power supply voltage to the output terminal. A third PMOS transistor outputs a second voltage lower than the power supply voltage to the output terminal. A well potential control section controls well voltages of the first and third transistors to be the power supply voltage where the power supply voltage and the second voltage are output to the output terminal, and controls the well voltages of the first and third transistors to be the first voltage where the first voltage is output to the output terminal.
摘要翻译：电压切换电路响应于选择信号从多个输入电压中选择电压，并从输出端输出所选择的电压。电压切换电路包括输出用于操作输出端子的逻辑电路的电源电压的第一PMOS晶体管。第二PMOS晶体管向输出端子输出高于电源电压的第一电压。第三PMOS晶体管将比电源电压低的第二电压输出到输出端子。阱电位控制部分将第一和第三晶体管的阱电压控制为将电源电压和第二电压输出到输出端的电源电压，并且将第一和第三晶体管的阱电压控制为第一电压，其中第一电压输出到输出端子。

5. 发明申请

US20070210776A1 Switching power source apparatus 审中-公开
标题翻译：开关电源装置
公开(公告)号：US20070210776A1
公开(公告)日：2007-09-13
申请号：US11704679
申请日：2007-02-08
申请人： Tomohiro Oka
发明人： Tomohiro Oka
IPC分类号： G05F1/00
CPC分类号： H02M3/156 , H02M1/44
摘要： There is provided a switching power supply device which is capable of reducing an influence of noises and also reducing a consumption current of a control circuit. A pseudo-random number generator circuit (12) generates random number data for determining frequencies of switching signals of MOS transistors (M1) and (M2). A chopping wave oscillation frequency (a frequency of a switching signal) of a chopping wave oscillator (3) randomly changes according to the random number data that is generated by the pseudo-random number generator circuit (12). A current control circuit (1) and a current control circuit (2) control consumption currents that flow in the chopping wave oscillator (3) and an error amplifier (8) according to a change (a change in the frequency of the switching signal) in the random number data that is generated by the pseudo-random number generator circuit (12).
摘要翻译：提供了能够减少噪声的影响并且还降低控制电路的消耗电流的开关电源装置。伪随机数发生器电路（12）产生用于确定MOS晶体管（M 1）和（M 2）的开关信号的频率的随机数数据。斩波振荡器（3）的斩波振荡频率（切换信号的频率）随着由伪随机数发生电路（12）生成的随机数数据而随机变化。电流控制电路（1）和电流控制电路（2）根据改变（切换信号的频率变化）控制在斩波振荡器（3）和误差放大器（8）中流动的消耗电流，在由伪随机数发生器电路（12）生成的随机数数据中。

6. 发明申请

US20100214011A1 BOOSTING CIRCUIT 有权
标题翻译：升压电路
公开(公告)号：US20100214011A1
公开(公告)日：2010-08-26
申请号：US12706992
申请日：2010-02-17
申请人： Ayaka Otani , Tomohiro Oka
发明人： Ayaka Otani , Tomohiro Oka
IPC分类号： G05F1/10
CPC分类号： H02M3/1584
摘要： Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.
摘要翻译：提供了一种避免与升压电路连接的外围电路的故障的升压电路。升压电路包括：第一放电电路，用于当升压单元停止升压操作时，对第一输出端子的电压进行放电; 以及用于对第二输出端子的电压进行放电的第二放电电路。当第二输出端子的电压和第一输出端子的电压之间的差电压等于或小于预定电压时，第二放电电路将第二输出端子的电压放电到第一输出端子的电位。

7. 发明申请

US20090190407A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090190407A1
公开(公告)日：2009-07-30
申请号：US12361620
申请日：2009-01-29
申请人： Yutaka Satou , Fumiyasu Utsunomiya , Tomohiro Oka
发明人： Yutaka Satou , Fumiyasu Utsunomiya , Tomohiro Oka
IPC分类号： G11C16/06 , G11C29/00
CPC分类号： G11C29/50 , G11C16/04 , G11C29/50004
摘要： Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltage portion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal and a voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; a comparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode.
摘要翻译：提供一种半导体存储器件，即使在通过与正电位的情况相似的测试方法的阈值电压为负电位的情况下也实现特性评估。半导体存储器件包括用于存储数据的多个存储单元。当输入测试信号时，半导体存储器件从正常模式改变为用于评估多个存储器单元的特性的测试模式。半导体存储装置还包括：存储单元选择部，用于选择存储单元; 用于产生参考电压的恒定电压部分; 用于产生参考电流的恒定电流部分; X开关电压切换控制电路，用于将X选择信号和从外部端子输入的电压信号中的一个提供给存储器单元的栅极; Y开关部分，用于将参考电流提供给由Y选择信号选择的存储器单元的漏极; 用于检测作为所述漏极的电压的漏极电压是否超过所述参考电压的比较器; 以及判定电平改变部分，用于调整参考电流的当前值和参考电压的电压值，以便基于测试模式中的控制信号来改变比较器的判定电平。

8. 发明授权

US08203378B2 Boosting circuit 有权
标题翻译：升压电路
公开(公告)号：US08203378B2
公开(公告)日：2012-06-19
申请号：US12706992
申请日：2010-02-17
申请人： Ayaka Otani , Tomohiro Oka
发明人： Ayaka Otani , Tomohiro Oka
IPC分类号： G05F1/10
CPC分类号： H02M3/1584
摘要： Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.
摘要翻译：提供了一种避免与升压电路连接的外围电路的故障的升压电路。升压电路包括：第一放电电路，用于当升压单元停止升压操作时，对第一输出端子的电压进行放电; 以及用于对第二输出端子的电压进行放电的第二放电电路。当第二输出端子的电压和第一输出端子的电压之间的差电压等于或小于预定电压时，第二放电电路将第二输出端子的电压放电到第一输出端子的电位。

9. 发明申请

US20100123512A1 Booster circuit 审中-公开
标题翻译：增压电路
公开(公告)号：US20100123512A1
公开(公告)日：2010-05-20
申请号：US12590950
申请日：2009-11-17
申请人： Yasushi Imai , Tomohiro Oka
发明人： Yasushi Imai , Tomohiro Oka
IPC分类号： G11C5/14 , H02M3/07
CPC分类号： H02M3/073 , G11C5/145 , G11C5/147 , H02M1/36
摘要： Provided is a booster circuit capable of shortening a boost rise time. A PMOS transistor is provided, as a switch circuit for controlling an operation of the booster circuit, between a boosted voltage output terminal and a voltage divider circuit in the booster circuit, and the PMOS transistor has a gate connected to a power supply terminal and a source and a back gate connected to the boosted voltage output terminal. Therefore, the PMOS transistor is turned off immediately after a start of a boosting operation, and hence an inverting input terminal of a comparator circuit is pulled down. Accordingly, the comparator circuit outputs a boosting operation signal, and the booster circuit immediately starts the boosting operation, with the result that the boost rise time may be shortened.
摘要翻译：提供了能够缩短升压时间的升压电路。提供PMOS晶体管，作为用于控制升压电路的运行的开关电路，在升压电路中的升压电压输出端子和分压电路之间，PMOS晶体管具有连接到电源端子和源极和连接到升压电压输出端子的背栅极。因此，在升压操作开始之后立即关断PMOS晶体管，因此比较器电路的反相输入端被拉下。因此，比较器电路输出升压操作信号，并且升压电路立即开始升压操作，结果可以缩短升压时间。

10. 发明申请

US20100013547A1 VOLTAGE SWITCHING CIRCUIT 有权
标题翻译：电压开关电路
公开(公告)号：US20100013547A1
公开(公告)日：2010-01-21
申请号：US12513976
申请日：2007-11-07
申请人： Tomohiro Oka
发明人： Tomohiro Oka
IPC分类号： G11C5/14
CPC分类号： H03K19/018521 , H03K19/0013 , H03K19/0016 , H03K2217/0018 , Y10T307/724 , Y10T307/858
摘要： Provided is a voltage switching circuit which outputs a voltage with low power consumption without lowering a plurality of voltages due to a threshold voltage of a transistor. The voltage switching circuit according to the present invention selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes: a first PMOS transistor for outputting a power supply voltage for operating a logic circuit of a semiconductor device to the output terminal; a second PMOS transistor for outputting a first voltage higher than the power supply voltage to the output terminal; a third PMOS transistor for outputting a second voltage lower than the power supply voltage to the output terminal; and a well potential control section for controlling well voltages of the first and third transistors to be the power supply voltage in a case of outputting the power supply voltage and the second voltage to the output terminal, and controlling the well voltages of the first and third transistors to be the first voltage in a case of outputting the first voltage to the output terminal.
摘要翻译：提供了一种电压切换电路，其输出低功耗的电压，而不会由于晶体管的阈值电压而降低多个电压。根据本发明的电压切换电路响应于选择信号从多个输入电压中选择电压，并从输出端输出所选择的电压。电压切换电路包括：第一PMOS晶体管，用于向输出端子输出用于操作半导体器件的逻辑电路的电源电压; 第二PMOS晶体管，用于向输出端子输出高于电源电压的第一电压; 第三PMOS晶体管，用于将低于电源电压的第二电压输出到输出端子; 以及井电位控制部分，用于在将所述电源电压和所述第二电压输出到所述输出端子的情况下，将所述第一和第三晶体管的阱电压控制为所述电源电压，并且控制所述第一和第三晶体管的阱电压在将第一电压输出到输出端子的情况下，晶体管成为第一电压。

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