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1. 发明授权

US08119503B2 Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby 有权
标题翻译：形成其中具有垂直半导体互连和二极管的集成电路器件的方法及由此形成的器件
公开(公告)号：US08119503B2
公开(公告)日：2012-02-21
申请号：US12498528
申请日：2009-07-07
申请人： Kong-Soo Lee , Kyoung-Seok Kim , Sang-Jin Park , Chang-Hoon Lee , Ji-Hyun Jeong , Jae-Hyun Park , Jae-Hee Oh
发明人： Kong-Soo Lee , Kyoung-Seok Kim , Sang-Jin Park , Chang-Hoon Lee , Ji-Hyun Jeong , Jae-Hyun Park , Jae-Hee Oh
IPC分类号： H01L47/00 , H01L21/20
CPC分类号： H01L27/1021 , H01L27/24 , H01L29/8613
摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。

2. 发明申请

US20100108971A1 Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby 有权
标题翻译：形成具有垂直半导体互连和二极管的集成电路器件的方法和由此形成的器件
公开(公告)号：US20100108971A1
公开(公告)日：2010-05-06
申请号：US12498528
申请日：2009-07-07
申请人： Kong-Soo Lee , Kyoung-Seok Kim , Sang-Jin Park , Chang-Hoon Lee , Ji-Hyun Jeong , Jae-Hyun Park , Jae-Hee Oh
发明人： Kong-Soo Lee , Kyoung-Seok Kim , Sang-Jin Park , Chang-Hoon Lee , Ji-Hyun Jeong , Jae-Hyun Park , Jae-Hee Oh
IPC分类号： H01L47/00 , H01L21/20
CPC分类号： H01L27/1021 , H01L27/24 , H01L29/8613
摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。

3. 发明授权

US08030129B2 Method of fabricating nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08030129B2
公开(公告)日：2011-10-04
申请号：US12655047
申请日：2009-12-21
申请人： Ji-Hyun Jeong , Jae-Hee Oh , Jae-Hyun Park
发明人： Ji-Hyun Jeong , Jae-Hee Oh , Jae-Hyun Park
IPC分类号： H01L21/06
CPC分类号： H01L27/24
摘要： A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.
摘要翻译：一种制造非易失性存储器件的方法，包括在下绝缘层上形成第一牺牲图案，所述第一牺牲图案具有沿第一方向延伸的第一开口，形成第二牺牲图案，所述第二牺牲图案具有在所述下绝缘层上沿第二方向延伸的第二开口，图案，其中所述第二开口与所述第一开口相交;使用所述第一和第二牺牲图案蚀刻所述下绝缘层，以形成具有由所述第一开口和所述第二开口相交的区域限定的接触孔的下绝缘图案，形成底部电极接触孔，并且在下绝缘图案上形成可变电阻图案，使得可变电阻图案的一部分连接到底电极的顶表面。

4. 发明授权

US08021966B2 Method fabricating nonvolatile memory device 有权
标题翻译：方法制造非易失性存储器件
公开(公告)号：US08021966B2
公开(公告)日：2011-09-20
申请号：US12644224
申请日：2009-12-22
申请人： Ji-Hyun Jeong , Jae-Hee Oh , Jae-Hyun Park
发明人： Ji-Hyun Jeong , Jae-Hee Oh , Jae-Hyun Park
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole.
摘要翻译：一种制造非易失性存储器件的方法包括：形成第一牺牲层图案，所述第一牺牲层图案包括在下电介质层上沿第一方向延伸的第一开口区域，形成包括使用所述第一牺牲层图案沿所述第一方向延伸的凹部的预下介电层图案，形成第二牺牲层图案牺牲层图案包括在预下电介质层图案和第一牺牲层图案上沿第二方向延伸的第二开口区域，其中第二开口区域与第一开放区域相交，形成包括间隔开的接触孔的下介电层图案在使用第一牺牲层图案和第二牺牲层图案的凹部中分开，其中接触孔延伸到下介电层图案的底部，并且在接触孔中形成底部电极。

5. 发明授权

US07651906B2 Integrated circuit devices having a stress buffer spacer and methods of fabricating the same 失效
标题翻译：具有应力缓冲垫片的集成电路器件及其制造方法
公开(公告)号：US07651906B2
公开(公告)日：2010-01-26
申请号：US11546120
申请日：2006-10-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
IPC分类号： H01L21/8234
CPC分类号： H01L27/24
摘要： Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。接触孔中有一个垂直二极管，在垂直二极管和绝缘层之间设有一个应力缓冲垫片。还提供了形成集成电路器件的方法。

6. 发明申请

US20090166600A1 INTEGRATED CIRCUIT DEVICES HAVING A STRESS BUFFER SPACER AND METHODS OF FABRICATING THE SAME 失效
标题翻译：具有应力缓冲器间隔器的集成电路装置及其制造方法
公开(公告)号：US20090166600A1
公开(公告)日：2009-07-02
申请号：US11546120
申请日：2006-10-11
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong , Sang-Jin Park
IPC分类号： H01L45/00 , H01L21/74
CPC分类号： H01L27/24
摘要： Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided.
摘要翻译：集成电路器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。接触孔中有一个垂直二极管，在垂直二极管和绝缘层之间设有一个应力缓冲垫片。还提供了形成集成电路器件的方法。

7. 发明授权

US08148193B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08148193B2
公开(公告)日：2012-04-03
申请号：US13236941
申请日：2011-09-20
申请人： Jae-Hyun Park , Jae-Hee Oh
发明人： Jae-Hyun Park , Jae-Hee Oh
IPC分类号： H01L21/00
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.
摘要翻译：诸如相变存储器件的半导体器件包括：半导体衬底，包括有源区，布置成暴露有源区的导电图案;设置在导电图案上的层间电介质图案，并且包括形成在暴露的有源区上的开口;以及接触孔与开口间隔开以暴露导电图案，半导体图案和电连接到暴露的有源区并且设置在开口中的加热器电极图案，连接到暴露的导电图案并被提供以填充接触孔的接触插塞以及设置在加热器电极图案上的相变材料层。

8. 发明授权

US07910912B2 Semiconductor devices having a planarized insulating layer 失效
标题翻译：具有平坦化绝缘层的半导体器件
公开(公告)号：US07910912B2
公开(公告)日：2011-03-22
申请号：US12612377
申请日：2009-11-04
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , B82Y10/00 , G11C13/0004 , G11C2213/79 , H01L21/76819 , H01L27/228 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.
摘要翻译：半导体器件包括设置在半导体衬底上的至少一个相变图案。依次层叠有平面化覆盖层，平坦化保护层和平坦化绝缘层，以包围至少一个相变图案的侧壁。互连层图案设置在平坦化覆盖层，平坦化保护层和平坦化绝缘层上。互连层图案与相变图案接触。

9. 发明申请

US20060237756A1 Phase change memory devices and their methods of fabrication 有权
公开(公告)号：US20060237756A1
公开(公告)日：2006-10-26
申请号：US11392310
申请日：2006-03-28
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L29/94
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

10. 发明申请

US20060011959A1 Semiconductor devices having a planarized insulating layer and methods of forming the same 失效
公开(公告)号：US20060011959A1
公开(公告)日：2006-01-19
申请号：US11184701
申请日：2005-07-19
申请人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Won-Cheol Jeong
IPC分类号： H01L29/94 , H01L21/4763 , H01L21/461
CPC分类号： G11C11/16 , B82Y10/00 , G11C13/0004 , G11C2213/79 , H01L21/76819 , H01L27/228 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

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