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1. 发明申请

US20100148311A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100148311A1
公开(公告)日：2010-06-17
申请号：US12635000
申请日：2009-12-10
申请人： Koji MIYATA , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
发明人： Koji MIYATA , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
IPC分类号： H01L23/544
CPC分类号： H01L24/83 , H01L23/544 , H01L24/31 , H01L2223/5442 , H01L2223/54426 , H01L2224/16 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/3512 , H01L2924/00 , H01L2224/0401
摘要： Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
摘要翻译：设置在基板的表面上的图案包括粘合区域图案和一个或多个非粘合区域图案。半导体芯片背面的芯片电极通过导电粘合剂附着在粘合区域图案上。因此，在本发明的基板中，与常规基板相比，在稳定状态下稳定的金镀层图案较小，导致成本降低。此外，芯片电极通过导电粘合剂以液体形式附着到粘附区域图案上。因此，与传统的半导体器件相比，本发明的半导体器件能够减少使用昂贵的导电粘合剂，从而降低成本。

2. 发明授权

US08269353B2 Semiconductor device having a plurality of adhesion area patterns and one or more non-adhesion area patterns 有权
标题翻译：具有多个粘附区域图案和一个或多个非粘合区域图案的半导体器件
公开(公告)号：US08269353B2
公开(公告)日：2012-09-18
申请号：US12635000
申请日：2009-12-10
申请人： Koji Miyata , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
发明人： Koji Miyata , Hiroyuki Nakanishi , Masahiro Okita , Kazuaki Tatsumi , Masato Yokobayashi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/83 , H01L23/544 , H01L24/31 , H01L2223/5442 , H01L2223/54426 , H01L2224/16 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/3512 , H01L2924/00 , H01L2224/0401
摘要： Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.
摘要翻译：设置在基板的表面上的图案包括粘合区域图案和一个或多个非粘合区域图案。半导体芯片背面的芯片电极通过导电粘合剂附着在粘合区域图案上。因此，在本发明的基板中，与常规基板相比，在稳定状态下稳定的金镀层图案较小，导致成本降低。此外，芯片电极通过导电粘合剂以液体形式附着到粘附区域图案上。因此，与传统的半导体器件相比，本发明的半导体器件能够减少使用昂贵的导电粘合剂，从而降低成本。

3. 发明申请

US20110042828A1 WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：接线板，半导体器件及制造半导体器件的方法
公开(公告)号：US20110042828A1
公开(公告)日：2011-02-24
申请号：US12988697
申请日：2009-03-16
申请人： Yoshiki Sota , Kazuaki Tatsumi
发明人： Yoshiki Sota , Kazuaki Tatsumi
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/49838 , H01L23/13 , H01L23/564 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H05K3/305 , H05K3/3452 , H05K2201/09072 , H05K2201/09772 , H05K2201/0989 , H05K2203/1178 , Y02P70/613 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015
摘要： A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
摘要翻译：本发明的布线基板（10）具备：贯通所述布线基板（10）的贯通孔（11b），设置在半导体芯片安装区域（15）中。以及设置在形成在半导体芯片安装区域（15）上的阻焊剂（9）上的通向通孔（11b）的凹槽图案（13）。上述构造使得可以经由凹槽图案（13）引导到通孔（11b），其收集在半导体芯片安装区域（15）中的湿气，并且因此有效地从半导体芯片安装区域排出水分（ 15）。因此，采用该布线基板（10）的半导体装置（30）在制造半导体装置（30）时由于加热而在其内部不会发生汽化膨胀，将半导体器件（30）安装在安装基板上。因此可以减少半导体器件的膨胀。

4. 发明授权

US08436456B2 Wiring board, semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：接线板，半导体器件及半导体器件的制造方法
公开(公告)号：US08436456B2
公开(公告)日：2013-05-07
申请号：US12988697
申请日：2009-03-16
申请人： Yoshiki Sota , Kazuaki Tatsumi
发明人： Yoshiki Sota , Kazuaki Tatsumi
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L23/49838 , H01L23/13 , H01L23/564 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45015 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H05K3/305 , H05K3/3452 , H05K2201/09072 , H05K2201/09772 , H05K2201/0989 , H05K2203/1178 , Y02P70/613 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/20752 , H01L2924/20753 , H01L2924/00015
摘要： A wiring board (10) of the present invention includes: a through hole (11b), provided in a semiconductor chip mounted region (15), penetrating the wiring board (10); and a groove pattern (13), provided on a solder resist (9) formed on the semiconductor chip mounted region (15), leading to the through hole (11b). The foregoing configuration makes it possible to guide, via the groove pattern (13) to the through hole (11b), moisture that collects in the semiconductor chip mounted region (15) and therefore to effectively discharge the moisture from the semiconductor chip mounted region (15). Thus, a semiconductor device (30) that employs the wiring board (10) does not suffer from vaporization and expansion, inside of it, due to heat that is applied at the time of manufacturing the semiconductor device (30) and at the time of mounting the semiconductor device (30) on a mount substrate. It is therefore possible to reduce expansion of the semiconductor device.
摘要翻译：本发明的布线基板（10）具备：贯通所述布线基板（10）的贯通孔（11b），设置在半导体芯片安装区域（15）中。以及设置在形成在半导体芯片安装区域（15）上的阻焊剂（9）上的通向通孔（11b）的凹槽图案（13）。上述构造使得可以经由凹槽图案（13）引导到通孔（11b），其收集在半导体芯片安装区域（15）中的湿气，并且因此有效地从半导体芯片安装区域排出水分（ 15）。因此，采用该布线基板（10）的半导体装置（30）在制造半导体装置（30）时由于加热而在其内部不会发生汽化膨胀，将半导体器件（30）安装在安装基板上。因此可以减少半导体器件的膨胀。

5. 发明授权

US4508953A Method of multi-layer welding 失效
标题翻译：多层焊接方法
公开(公告)号：US4508953A
公开(公告)日：1985-04-02
申请号：US487687
申请日：1983-04-22
申请人： Tsudoi Murakami , Shoji Nasu , Kazuaki Tatsumi , Yasuhide Nagahama
发明人： Tsudoi Murakami , Shoji Nasu , Kazuaki Tatsumi , Yasuhide Nagahama
IPC分类号： B23K9/02 , B23K9/12
CPC分类号： B23K9/0216
摘要： A method of multi-layer welding in which the welding operation is performed according to a path of welding defined by interpolating a plurality of instructed points by a suitable line, the method being characterized by storing in a memory device the coordinates actually passed by a welding torch in the welding operation of the first layer at the instructed points and determining the welding path of the second and succeeding layers by adding a predetermined amount of shift to the actual detected coordinates stored in the memory device at the instructed points and interpolating the shifted coordinates by a suitable line. According to another aspect of the present invention, therefor provided is a method for controlling the locus of operation in the second and succeeding layers in a multi-layer welding operation by a teach/playback type robot including an arithmetic control mechanism the method being characterized by teaching an arcuate locus of operation of the first layer; utilizing as a parameter a shift width corresponding to the arcuate bead to be formed in the second and succeeding layers through an external input member; determining the direction of shift of the second and succeeding layers by calculating the inner product of the directional vector of a welding torch according to the teaching data of the first layer and a directional vector from a point on the arcuate locus of operation to the center of the arc; and calculating the locus of operation of the second or a succeeding layer from the shift direction and width by the arithmetic control mechanism.
摘要翻译：一种多层焊接方法，其中根据通过适当的线插入多个指示点所限定的焊接路径执行焊接操作，该方法的特征在于，在存储装置中存储通过焊接实际通过的坐标在指示点处焊接第一层的焊炬，并且通过在指示点处对存储在存储装置中的实际检测到的坐标加上预定量的位移来确定第二层和后层的焊接路径，并且内插移位的坐标通过合适的线。根据本发明的另一方面，提供了一种用于通过包括算术控制机构的教导/重放型机器人在多层焊接操作中控制第二层和后层中的操作轨迹的方法，该方法的特征在于教授第一层的弧形轨迹; 利用与通过外部输入构件形成在第二层和后层中的弓形凸缘相对应的移位宽度作为参数; 通过根据第一层的教学数据计算焊炬的方向矢量的内积和从弓形操作轨迹上的点到方向矢量的方向矢量来确定第二层和后层的移位方向电弧并且通过算术控制机构从移位方向和宽度计算第二层或后层的工作轨迹。

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