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1. 发明申请

US20090172309A1 Apparatus and method for controlling queue 审中-公开
标题翻译：控制队列的装置和方法
公开(公告)号：US20090172309A1
公开(公告)日：2009-07-02
申请号：US12285746
申请日：2008-10-14
申请人： Koji Kobayashi , Takashi Hagiwara , Yasushi Kanoh
发明人： Koji Kobayashi , Takashi Hagiwara , Yasushi Kanoh
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F2212/1016 , G06F2212/1028 , Y02D10/13
摘要： An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which changes an order of the store and load requests so that the order includes a string of the store requests and a string of the load requests.
摘要翻译：一种装置包括一个队列元素，该队列存储要发给存储装置的多个存储器访问请求，存储器访问请求包括存储请求和加载请求，以及控制器，其改变存储和加载请求的顺序，使得该顺序包括一个存储请求的字符串和一个负载请求的字符串。

2. 发明授权

US09053030B2 Cache memory and control method thereof with cache hit rate 有权
标题翻译：缓存内存及其控制方法，具有缓存命中率
公开(公告)号：US09053030B2
公开(公告)日：2015-06-09
申请号：US13144820
申请日：2010-01-25
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/0842
摘要： A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array.
摘要翻译：缓存存储器包括存储兑现块的数据阵列; 存储缓存块的地址的第一地址数组; 第二地址阵列，当高速缓存未命中时，存储要从数据阵列移除的第一块的地址; 以及控制单元，当存储在第二地址阵列中的地址在导致高速缓存未命中的第二块之前的周期期间导致高速缓存命中时，向处理器发送存储在数据阵列中的第一块作为高速缓存命中块从内存读取并写入数据数组。

3. 发明申请

US20120102271A1 CACHE MEMORY SYSTEM AND CACHE MEMORY CONTROL METHOD 审中-公开
标题翻译：缓存记忆系统和缓存记忆控制方法
公开(公告)号：US20120102271A1
公开(公告)日：2012-04-26
申请号：US13148896
申请日：2010-01-15
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F12/12
CPC分类号： G06F12/0864 , G06F12/12
摘要： The number of ways of address arrays (102, 103, and 104) is made greater than the number of ways of data arrays (105 and 106). At the time of a mishit, a request is issued to read from memory (3) block data of the address of the mishit and the address in an address entry of an available address array. At this time, the address entry of an address array and the data entry of a data array that correspond to block data to be replaced are kept valid until the arrival of the block data corresponding to the read request in cache memory system (1) from memory (3). Therefore, access from CPU (2) to block data to be replaced can be handled as a cache hit when access occurs before the block data corresponding to the read request arrive in the cache memory system (1) from memory 3.
摘要翻译：地址阵列（102,103和104）的方式数量大于数据阵列（105和106）的路数。在虚拟时，发出从存储器（3）读取地址的数据和可用地址阵列的地址条目中的地址的请求。此时，地址列表的地址条目和与要替换的块数据相对应的数据阵列的数据条目保持有效，直到对应于读取请求的块数据到达高速缓冲存储器系统（1）记忆（3）。因此，当从存储器3到达高速缓冲存储器系统（1）之前，当与读取的请求相对应的块数据到达存储器3之前，当访问发生时，CPU（2）到块被替换的块的访问可被当作高速缓存命中来处理。

4. 发明授权

US06678722B1 Interprocessor communication system for parallel processing 有权
标题翻译：处理器间并行处理通信系统
公开(公告)号：US06678722B1
公开(公告)日：2004-01-13
申请号：US09568593
申请日：2000-05-11
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F15167
CPC分类号： G06F15/17331
摘要： The present invention is directed to providing an interprocessor communication system capable of obviating degradation of the performance in an interprocessor communication caused by the processing to avoid a page fault. In this system, a source processor transmits a check packet directly after successive data is transmitted by the interprocessor communication, to confirm whether or not a page fault takes place on the receiver side. The source processor carries out no processing in the case that no page fault takes place, and, in the case that a page fault takes place, the data in the page-faulty page is retransmitted. The destination processor stores the logical page numbers of the page-faulty pages in the main memory to utilize the data retransmission. Furthermore, the destination processor confirms whether or not the page faults occur in the identical page and if that is the case, no interrupt is raised so as to avoid too frequent interrupts.
摘要翻译：本发明旨在提供一种处理器间通信系统，其能够避免由处理引起的处理器间通信中的性能下降，以避免页面故障。在该系统中，源处理器在通过处理器间通信发送连续数据之后直接发送校验分组，以确认在接收机侧是否发生寻呼故障。在不发生页面错误的情况下，源处理器不执行处理，并且在发生页面错误的情况下，重新发送页面错误页面中的数据。目的处理器将页面故障页面的逻辑页码存储在主存储器中以利用数据重传。此外，目的处理器确认页错误是否发生在相同的页面中，如果是这种情况，则不会引起中断，以避免过多的中断。

5. 发明授权

US06341313B1 Flow controlling method and apparatus for network between processors 有权
标题翻译：处理器之间网络的流量控制方法和装置
公开(公告)号：US06341313B1
公开(公告)日：2002-01-22
申请号：US09241075
申请日：1999-02-01
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F1516
CPC分类号： G06F15/17393 , G06F5/06
摘要： A packet switch provides a write signal when processing of a packet in a FIFO memory is started, and outputs the write signal to the preceding stage. Meanwhile, the writing side manages whether a FIFO memory in the next stage is in a write-enabled state, and renders it into a write-disabled state in response to writing of a packet. The writing side also renders the FIFO memory of the next stage into a write-enabled state in response to a write-enable signal from the next stage.
摘要翻译：分组交换机在FIFO存储器中的分组的处理开始时提供写入信号，并将写信号输出到前一级。同时，写入侧管理下一级的FIFO存储器是否处于写使能状态，并且响应于数据包的写入而使其成为写禁止状态。响应于来自下一级的写使能信号，写入端还使下一级的FIFO存储器进入写使能状态。

6. 发明授权

US6101551A Multi-processor system for supporting multicasting communication and inter-multiprocessor communication method therefor 失效
标题翻译：用于支持多播通信的多处理器系统和多处理器间通信方法
公开(公告)号：US6101551A
公开(公告)日：2000-08-08
申请号：US845766
申请日：1997-04-28
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F15/17
摘要： A packet is held in a FIFO memory through a network. The packet includes a header and data. The header includes fields of a packet type, a data length, and a designation for a processor. The packet type field defines whether its packet is either a single-cast packet or a multi-cast packet and a designation method for a destination address. There are several methods for the destination address: first, a method using a message buffer in a memory, secondly, a method using a value of an address register previously set, and thirdly, a method designating as a destination address. The (original) entity of the address register may be reserved in the memory. In this case, different message buffers for every task identifier may also be reserved in the memory.
摘要翻译：数据包通过网络保存在FIFO存储器中。分组包括报头和数据。报头包括分组类型，数据长度和处理器的指定的字段。分组类型字段定义其分组是单播分组还是多播分组，以及目的地址的指定方法。目的地地址有几种方法：首先，使用存储器中的消息缓冲器的方法，其次，使用先前设置的地址寄存器的值的方法，以及指定作为目的地地址的方法。地址寄存器的（原始）实体可以保留在存储器中。在这种情况下，也可以在存储器中保留用于每个任务标识符的不同消息缓冲器。

7. 发明申请

US20110283041A1 CACHE MEMORY AND CONTROL METHOD THEREOF 有权
标题翻译：缓存记忆及其控制方法
公开(公告)号：US20110283041A1
公开(公告)日：2011-11-17
申请号：US13144820
申请日：2010-01-25
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F12/08
CPC分类号： G06F12/0842
摘要： A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array.
摘要翻译：缓存存储器包括存储兑现块的数据阵列; 存储缓存块的地址的第一地址数组; 第二地址阵列，当高速缓存未命中时，存储要从数据阵列移除的第一块的地址; 以及控制单元，当存储在第二地址阵列中的地址在导致高速缓存未命中的第二块之前的周期期间导致高速缓存命中时，向处理器发送存储在数据阵列中的第一块作为高速缓存命中块从内存读取并写入数据数组。

8. 发明申请

US20110216860A1 COMMUNICATION METHOD 有权
标题翻译：通信方法
公开(公告)号：US20110216860A1
公开(公告)日：2011-09-08
申请号：US12673727
申请日：2008-04-09
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： H04L7/00
CPC分类号： G06F15/17393 , G06F9/522
摘要： A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase.
摘要翻译：提供通信方法以减少集体通信中的通信阶段的处理器间同步的开销，并加速集体通信。并行计算机中的每个处理器在通过处理器间网络在处理器之间同时执行通信的集体通信阶段之前开始先前的处理。每个处理器在预定时间t的前一处理的一部分剩余时，预先执行同步命令。如果满足同步条件，则处理器间同步控制部分向每个处理器发送同步完成通知。在此期间，每个处理器并行执行上一个进程。然后，多个处理器进入集体通信阶段。

9. 发明申请

US20090307463A1 INTER-PROCESSOR, COMMUNICATION SYSTEM, PROCESSOR, INTER-PROCESSOR COMMUNICATION METHOD, AND COMMUNICATION METHOD 审中-公开
标题翻译：交互处理器，通信系统，处理器，交互处理器通信方法和通信方法
公开(公告)号：US20090307463A1
公开(公告)日：2009-12-10
申请号：US12437880
申请日：2009-05-08
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F15/76 , H04L12/56 , G06F9/06 , G06F9/46
CPC分类号： G06F13/385 , G06F15/17318
摘要： An inter-processor communication system includes processors and a transfer device that, upon receiving a multicast packet from any of the processors, transfers the packet to processors designated in the packet as destinations among the processors. Each processor includes: a memory unit; a holding unit which holds position information indicating a reference position in the memory unit; a transmitting unit which transmits to the transfer device a multicast packet representing data and an adjustment value indicating an area for writing data that was set for use by its own processor by using the reference position; and a receiving unit which, upon receiving a multicast packet that has been transmitted by way of the transfer device, determines a write position in the memory unit based on the adjustment value in the packet and the position information and stores the data in the packet in that write position.
摘要翻译：处理器间通信系统包括处理器和传送设备，其在从任何处理器接收到多播分组时，将分组传送到处理器中作为目的地的分组中指定的处理器。每个处理器包括：存储器单元; 保持单元，其保持指示存储单元中的参考位置的位置信息; 发送单元，其向所述传送设备发送表示数据的多播分组，以及指示用于写入数据的区域的调整值，所述区域被设置为通过使用所述参考位置由其自己的处理器使用; 以及接收单元，其在接收到通过所述传送设备发送的多播分组时，基于分组中的调整值和所述位置信息来确定所述存储器单元中的写入位置，并将所述数据存储在所述分组中那个写位置

10. 发明授权

US09195629B2 Data transfer system 有权
标题翻译：数据传输系统
公开(公告)号：US09195629B2
公开(公告)日：2015-11-24
申请号：US13213371
申请日：2011-08-19
申请人： Yasushi Kanoh
发明人： Yasushi Kanoh
IPC分类号： G06F13/14 , G06F15/173 , H04L12/835 , H04L12/801
CPC分类号： G06F15/17325 , G06F13/14 , H04L47/17 , H04L47/30
摘要： A data transfer system includes: a plurality of processors; and a plurality of data transfer units that executes a data transfer from one processor to another processor via a plurality of input ports and a plurality of output ports. The data transfer unit includes: an arbitration unit that executes arbitration of conflicting data sent to a same next destination; and a strength information notification unit that sends strength information indicating a number of conflicts of the arbitrated conflicting data to the next destination. The arbitration unit decides a selection ratio, which is a ratio of selecting each of the input ports and receiving the conflicting data from the selected input port, according to a ratio between the input ports in relation to a magnitude of the number of conflicts indicated by the strength information received from each of the input ports.
摘要翻译：数据传输系统包括：多个处理器; 以及多个数据传送单元，其经由多个输入端口和多个输出端口执行从一个处理器到另一个处理器的数据传送。数据传送单元包括：仲裁单元，执行发送到同一下一个目的地的冲突数据的仲裁; 以及强度信息通知单元，其向下一个目的地发送指示所述冲突数据冲突的数量的强度信息。仲裁单元根据输入端口之间的比例来确定选择比率，该比率是选择每个输入端口并从所选择的输入端口接收冲突数据，该比例与由从每个输入端口接收的强度信息。

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