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1. 发明授权

US08924606B2 Storage system and data transfer control method 有权
标题翻译：存储系统和数据传输控制方法
公开(公告)号：US08924606B2
公开(公告)日：2014-12-30
申请号：US13395807
申请日：2012-03-02
申请人： Koji Akiyama , Susumu Tsuruta , Hideaki Fukuda , Hiroshi Shimmura , Shoji Kato
发明人： Koji Akiyama , Susumu Tsuruta , Hideaki Fukuda , Hiroshi Shimmura , Shoji Kato
IPC分类号： G06F13/28 , G06F3/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0689
摘要： It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.
摘要翻译：提供了一种用于根据来自主计算机的请求输入和输出数据的存储系统，包括：用于处理请求输入或输出的数据的至少一个处理器; 用于在存储系统中的存储器之间传送数据的多个传送控制器; 以及至少一个传送定序器，用于根据来自处理器的指令向多个传送控制器请求数据传送。处理器向至少一个传送定序器发送一系列数据传送请求。所述至少一个传送定序器基于所述一系列数据传送请求来请求对所述多个传送控制器中的每一个的数据传送。每个传送控制器根据来自至少一个传送定序器的指令在存储器之间传送数据。

2. 发明申请

US20130232284A1 STORAGE SYSTEM AND DATA TRANSFER CONTROL METHOD 有权
标题翻译：存储系统和数据传输控制方法
公开(公告)号：US20130232284A1
公开(公告)日：2013-09-05
申请号：US13395807
申请日：2012-03-02
申请人： Koji Akiyama , Susumu Tsuruta , Hideaki Fukuda , Hiroshi Shimmura , Shoji Kato
发明人： Koji Akiyama , Susumu Tsuruta , Hideaki Fukuda , Hiroshi Shimmura , Shoji Kato
IPC分类号： G06F13/28
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0689
摘要： It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.
摘要翻译：提供了一种用于根据来自主计算机的请求输入和输出数据的存储系统，包括：用于处理请求输入或输出的数据的至少一个处理器; 用于在存储系统中的存储器之间传送数据的多个传送控制器; 以及至少一个传送定序器，用于根据来自处理器的指令向多个传送控制器请求数据传送。处理器向至少一个传送定序器发送一系列数据传送请求。所述至少一个传送定序器基于所述一系列数据传送请求来请求对所述多个传送控制器中的每一个的数据传送。每个传送控制器根据来自至少一个传送定序器的指令在存储器之间传送数据。

3. 发明授权

US08694698B2 Storage system and method for prioritizing data transfer access 失效
标题翻译：用于优先处理数据传输访问的存储系统和方法
公开(公告)号：US08694698B2
公开(公告)日：2014-04-08
申请号：US13503489
申请日：2012-04-12
申请人： Makio Mizuno , Masanori Takada , Tomohiro Yoshihara , Susumu Tsuruta
发明人： Makio Mizuno , Masanori Takada , Tomohiro Yoshihara , Susumu Tsuruta
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0689
摘要： According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently.
摘要翻译：根据存储子系统的现有技术的数据传输方法，当发生数据传输访问的竞争时，均匀地分配空闲接入目的端口，而不确定接入目的地的接入类型或接入状态，使得设备的性能没有增强。本发明通过基于访问类型或竞争性数据传送访问的剩余传送数据量，或者通过改变访问备用数据传送访问的访问目的地，选择优先完成数据传输的数据传送访问，从而解决了这个问题，从而高效地执行数据传输。

4. 发明申请

US20100057948A1 Storage control apparatus 有权
标题翻译：存储控制装置
公开(公告)号：US20100057948A1
公开(公告)日：2010-03-04
申请号：US12289004
申请日：2008-10-17
申请人： Masateru Hemmi , Susumu Tsuruta , Daisuke Isobe
发明人： Masateru Hemmi , Susumu Tsuruta , Daisuke Isobe
IPC分类号： G06F3/00
CPC分类号： G06F3/0634 , G06F3/0625 , G06F3/0689 , Y02D10/154
摘要： A storage control apparatus capable of reducing a power consumption in network port units, including a host communication control unit 10 which includes a plurality of network ports 18 and which controls communications with a host computer 2 that is connectable through the network ports, a storage-device communication control unit 16 which controls communications with a plurality of storage devices, a plurality of DMA portions 111 by which data to be transmitted/received between the host computer and the storage devices are transferred between the host communication control unit 10 and the storage-device communication control unit 16, a plurality of cache memories 12 in which the data to be transferred by the DMA portions 111 are temporarily stored, and a power saving control portion 110 which stops the DMA portion 111 and the cache memory 12 that are previously associated with one network port, on the basis of a connection situation of the pertinent network port with the host computer and a data rate to be inputted/outputted to/from the pertinent port.
摘要翻译：一种能够降低网络端口单元的功耗的存储控制装置，包括主机通信控制单元10，主机通信控制单元10包括多个网络端口18，并且控制与主机计算机2通过网络端口连接的通信; 控制与多个存储装置的通信的装置通信控制单元16，在主机通信控制单元10和存储装置10之间传送在主计算机和存储装置之间要发送/接收的数据的多个DMA部分111，设备通信控制单元16，其中临时存储要由DMA部分111传送的数据的多个高速缓存存储器12以及停止先前相关联的DMA部分111和高速缓冲存储器12的省电控制部分110 根据与主机相关的网络端口的连接情况，使用一个网络端口以及要从相关端口输入/输出的数据速率。

5. 发明授权

US07526592B2 Interrupt control system and storage control system using the same 有权
标题翻译：中断控制系统和存储控制系统使用相同
公开(公告)号：US07526592B2
公开(公告)日：2009-04-28
申请号：US11604690
申请日：2006-11-28
申请人： Susumu Tsuruta
发明人： Susumu Tsuruta
IPC分类号： G06F13/24 , G06F13/38
CPC分类号： G06F13/4027 , G06F13/24
摘要： An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.
摘要翻译：提供一种中断控制系统，其中基于信号线的中断系统可以结合到使用MSI（消息信号中断）的中断控制中。中断控制系统包括第一PCI接口，第二PCI接口，用作第一PCI接口和第二PCI接口之间桥接的PCI桥，以及用于控制中断信号的控制电路。 PCI桥接器识别从第一PCI接口发送到第二PCI接口的消息信号中断，并将消息信号中断传送到控制电路，并且控制电路设置有用于将消息信号中断转换为中断的中断转换单元信号并通过信号线输出。

6. 发明授权

US07996712B2 Data transfer controller, data consistency determination method and storage controller 有权
标题翻译：数据传输控制器，数据一致性确定方法和存储控制器
公开(公告)号：US07996712B2
公开(公告)日：2011-08-09
申请号：US12081746
申请日：2008-04-21
申请人： Susumu Tsuruta
发明人： Susumu Tsuruta
IPC分类号： G06F11/00
CPC分类号： G06F11/1004 , G06F11/1008 , G06F12/0802
摘要： A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area of the cache memory. First check data is created and stored for each block. A data consistency determination module reads out the data from the cache memory subsequent to the end of a data write, and creates second check data anew. By comparing the second check data against the first check data, it can be determined whether or not the data has been stored normally in the cache memory. The data consistency determination module can also determine the consistency of the data on the basis of the data address written to the cache memory.
摘要翻译：本发明的数据传送控制器即使在数据没有按顺序传送到高速缓存存储器的情况下也可以确定数据是否已被正确地存储在高速缓冲存储器中。从主机输入的数据被传送到高速缓冲存储器的规定区域并被存储。为每个块创建和存储第一个检查数据。数据一致性确定模块在数据写入结束之后从高速缓冲存储器读出数据，并重新创建第二检查数据。通过将第二检查数据与第一检查数据进行比较，可以确定数据是否已经正常存储在高速缓冲存储器中。数据一致性确定模块还可以基于写入高速缓冲存储器的数据地址来确定数据的一致性。

7. 发明申请

US20110153884A1 Storage system provided with function for detecting write completion 有权
标题翻译：具有检测写入完成功能的存储系统
公开(公告)号：US20110153884A1
公开(公告)日：2011-06-23
申请号：US12308574
申请日：2008-11-25
申请人： Suguru Shimotaya , Susumu Tsuruta , Daisuke Isobe
发明人： Suguru Shimotaya , Susumu Tsuruta , Daisuke Isobe
IPC分类号： G06F13/42
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0635 , G06F3/0689 , H04L67/1097
摘要： It is an object to prevent a processing speed of the storage system provided with a function for detecting a write completion of data from being reduced.A controller module is provided with at least one processor module, at least one storage resource, and at least one transfer control module connected to the processor module and the storage resource. The transfer control module is provided with a receiver and a transmitter. The receiver receives a write packet from the processor module, includes a specific code in the write packet, and then transmits the write packet. In the case in which the transmitter receives a write packet and the received write packet includes the specific code, the transmitter writes targeted data in the write packet to the storage resource to be written, generates a response packet that is a response indicating a completion of a write, and transmits the generated response packet.
摘要翻译：本发明的目的是防止具有检测数据写入完成功能的存储系统的处理速度降低。控制器模块设置有至少一个处理器模块，至少一个存储资源以及连接到处理器模块和存储资源的至少一个传输控制模块。传送控制模块设置有接收器和发射器。接收器从处理器模块接收写入包，在写入包中包含特定的代码，然后发送写入包。在发送器接收到写入包并且接收到的写入包包含特定代码的情况下，发送器将写入包中的目标数据写入要写入的存储资源，生成作为响应指示完成的响应的响应包写入，并发送生成的响应包。

8. 发明申请

US20060059302A1 Disk array subsystem 审中-公开
标题翻译：磁盘阵列子系统
公开(公告)号：US20060059302A1
公开(公告)日：2006-03-16
申请号：US10983583
申请日：2004-11-09
申请人： Susumu Tsuruta
发明人： Susumu Tsuruta
IPC分类号： G06F13/00
CPC分类号： G06F13/387 , G06F3/0601 , G06F2003/0692
摘要： There is a technique for a disk array subsystem which can reduce the number of LSIs required per one channel and mount more channels on a package, in a package of a channel control unit. In the disk array subsystem, a channel control unit receiving a data input/output request from an external unit has: a plurality of link control LSIs establishing communication with the external unit; a plurality of processors (MP) processing the data input/output command from the external unit; and a channel control LSI having a bridge control unit for changing a plurality of buses respectively connected to the link control LSIs and processors, connecting the bus connected to the link control LSI and the bus connected to the processor by the bridge control unit, and transferring the data between the link control LSI and the cache memory in accordance with the processor.
摘要翻译：存在磁盘阵列子系统的技术，其可以在通道控制单元的封装中减少每个通道所需的LSI的数量并且在封装上安装更多的通道。在磁盘阵列子系统中，从外部单元接收数据输入/输出请求的信道控制单元具有与外部单元建立通信的多个链路控制LSI; 多个处理器（MP），从外部单元处理数据输入/输出命令; 以及通道控制LSI，具有桥接控制单元，用于改变分别连接到链路控制LSI和处理器的多个总线，连接到链路控制LSI的总线和由桥接控制单元连接到处理器的总线，以及传送根据处理器在链路控制LSI和高速缓冲存储器之间的数据。

9. 发明授权

US06988151B2 Storage control device with a plurality of channel control sections 失效
标题翻译：具有多个通道控制部的存储控制装置
公开(公告)号：US06988151B2
公开(公告)日：2006-01-17
申请号：US10809740
申请日：2004-03-24
申请人： Susumu Tsuruta
发明人： Susumu Tsuruta
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/28
摘要： A storage control device provided with a plurality of channel control sections for receiving data input and output requests from an information processing device and transmitting and receiving data, to and from an information processing device, each of the plurality of channel control sections comprising: an input/output control section for receiving data input and output requests from the information processing device and controlling transmission and reception of data between a data storage memory and the information processing device; a processor; a data storage memory; and a data transfer device for transferring data in the data storage memory to a cache memory; and in a first channel control section of the plurality of channel control sections, the processor manages the data storage space in the data storage memory, and in a second channel control section, the input/output control section manages the data storage space in the data storage memory, and reports information relating to the data storage space to the processor.
摘要翻译：一种存储控制装置，具有多个信道控制部分，用于从信息处理设备接收数据输入和输出请求，并向信息处理设备发送数据，并从信息处理设备接收数据，所述信道控制部分包括：输入 /输出控制部分，用于从信息处理设备接收数据输入和输出请求，并控制数据存储存储器和信息处理设备之间的数据传输和接收; 处理器数据存储器; 以及用于将数据存储存储器中的数据传送到高速缓冲存储器的数据传送装置; 并且在多个信道控制部的第一信道控制部中，处理器管理数据存储存储器中的数据存储空间，在第二信道控制部中，输入/输出控制部管理数据中的数据存储空间存储存储器，并将与数据存储空间相关的信息报告给处理器。

10. 发明授权

US07953904B2 Storage control apparatus having power saving controller which stops particular data transfers based on connection and data transfer rates 有权
标题翻译：具有省电控制器的存储控制装置，其基于连接和数据传输速率停止特定的数据传送
公开(公告)号：US07953904B2
公开(公告)日：2011-05-31
申请号：US12289004
申请日：2008-10-17
申请人： Masateru Hemmi , Susumu Tsuruta , Daisuke Isobe
发明人： Masateru Hemmi , Susumu Tsuruta , Daisuke Isobe
IPC分类号： G03F3/00
CPC分类号： G06F3/0634 , G06F3/0625 , G06F3/0689 , Y02D10/154
摘要： A storage control apparatus capable of reducing a power consumption in network port units, including a host communication control unit 10 which includes a plurality of network ports 18 and which controls communications with a host computer 2 that is connectable through the network ports, a storage-device communication control unit 16 which controls communications with a plurality of storage devices, a plurality of DMA portions 111 by which data to be transmitted/received between the host computer and the storage devices are transferred between the host communication control unit 10 and the storage-device communication control unit 16, a plurality of cache memories 12 in which the data to be transferred by the DMA portions 111 are temporarily stored, and a power saving control portion 110 which stops the DMA portion 111 and the cache memory 12 that are previously associated with one network port, on the basis of a connection situation of the pertinent network port with the host computer and a data rate to be inputted/outputted to/from the pertinent port.
摘要翻译：一种能够降低网络端口单元的功耗的存储控制装置，包括主机通信控制单元10，主机通信控制单元10包括多个网络端口18，并且控制与主机计算机2通过网络端口连接的通信; 控制与多个存储装置的通信的装置通信控制单元16，在主机通信控制单元10和存储装置10之间传送在主计算机和存储装置之间要发送/接收的数据的多个DMA部分111，设备通信控制单元16，其中临时存储要由DMA部分111传送的数据的多个高速缓存存储器12以及停止先前相关联的DMA部分111和高速缓冲存储器12的省电控制部分110 基于与主机相关的网络端口的连接情况，具有一个网络端口以及要从相关端口输入/输出的数据速率。

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