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1. 发明授权

US07368767B2 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential 失效
标题翻译：半导体集成电路器件通过使用标准单元自动布线布线形成，并设计方法固定其良好的电位
公开(公告)号：US07368767B2
公开(公告)日：2008-05-06
申请号：US11087597
申请日：2005-03-24
申请人： Koichi Kinoshita , Yasuhito Itaka , Takeshi Sugahara
发明人： Koichi Kinoshita , Yasuhito Itaka , Takeshi Sugahara
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , H01L27/0207 , Y10S257/909
摘要： A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.
摘要翻译：从库中读取标准单元并执行自动布局布线，从而构成电路。接下来，搜索配置的电路中的每个单元格列的空白区域。在搜索的单元格列中的空白区域中，放置间隔单元或填充单元。此时，使用间隔电池或填充电池，电池列中的标准电池的阱电位是固定的。

2. 发明授权

US07882476B2 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential 有权
标题翻译：半导体集成电路器件通过使用标准单元自动布线布线形成，并设计方法固定其良好的电位
公开(公告)号：US07882476B2
公开(公告)日：2011-02-01
申请号：US11886928
申请日：2005-09-15
申请人： Yasuhito Itaka , Koichi Kinoshita , Takeshi Sugahara
发明人： Yasuhito Itaka , Koichi Kinoshita , Takeshi Sugahara
IPC分类号： G06F17/50 , H01L27/118 , H01L27/092
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/11807
摘要： Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.
摘要翻译：从库和电路读取不具有阱电位固定有源区（4T-11至4T-14,4T-21至4T-24,4T-31至4T-34,4T-41至4T-44）的标准单元是通过自动布局布线临时设计的。然后，从暂时设计的电路中的相同定时的晶体管的数量中的至少一个，晶体管的尺寸，转移概率和出现概率来估计衬底电位的变化。确定基板电位的估计变化是否在参考值内。如果估计的衬底电位变化超过参考值，则从库中读出具有阱电位固定有源区（2T-11,2T-21,2T-31和2T-41）的标准电池，放置在区域其中估计的衬底电位变化超过参考值。此后，再次进行自动布局布线，从而形成电路。

3. 发明申请

US20090083686A1 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential 有权
标题翻译：半导体集成电路器件通过使用标准单元自动布线布线形成，并设计方法固定其良好的电位
公开(公告)号：US20090083686A1
公开(公告)日：2009-03-26
申请号：US11886928
申请日：2005-09-15
申请人： Yasuhito Itaka , Koichi Kinoshita , Takeshi Sugahara
发明人： Yasuhito Itaka , Koichi Kinoshita , Takeshi Sugahara
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/11807
摘要： Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporarily designed by automatic layout wiring. Then, a change in the substrate potential is estimated from at least one of the number of transistors to be switched at the same timing in the temporarily designed circuit, the sizes of transistors, the transition probability, and the appearance probability. It is determined whether the estimated change in the substrate potential is within a reference value. If the estimated change in the substrate potential has exceeded the reference value, standard cells with a well potential fixing active region (2T-11, 2T-21, 2T-31 and 2T-41) are read from the library and placed in a region where the estimated change in the substrate potential exceeds the reference value. Thereafter, automatic layout wiring is done again, thereby forming a circuit.
摘要翻译：从库和电路读取不具有阱电位固定有源区（4T-11至4T-14,4T-21至4T-24,4T-31至4T-34,4T-41至4T-44）的标准单元是通过自动布局布线临时设计的。然后，从暂时设计的电路中的相同定时的晶体管的数量中的至少一个，晶体管的尺寸，转移概率和出现概率来估计衬底电位的变化。确定基板电位的估计变化是否在参考值内。如果估计的衬底电位变化超过参考值，则从库中读出具有阱电位固定有源区（2T-11,2T-21,2T-31和2T-41）的标准电池，放置在区域其中估计的衬底电位变化超过参考值。此后，再次进行自动布局布线，从而形成电路。

4. 发明申请

US20060131609A1 Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential 失效
标题翻译：半导体集成电路器件通过使用标准单元自动布线布线形成，并设计方法固定其良好的电位
公开(公告)号：US20060131609A1
公开(公告)日：2006-06-22
申请号：US11087597
申请日：2005-03-24
申请人： Koichi Kinoshita , Yasuhito Itaka , Takeshi Sugahara
发明人： Koichi Kinoshita , Yasuhito Itaka , Takeshi Sugahara
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , H01L27/0207 , Y10S257/909
摘要： A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.
摘要翻译：从库中读取标准单元并执行自动布局布线，从而构成电路。接下来，搜索配置的电路中的每个单元格列的空白区域。在搜索的单元格列中的空白区域中，放置间隔单元或填充单元。此时，使用间隔电池或填充电池，电池列中的标准电池的阱电位是固定的。

5. 发明授权

US07514728B2 Semiconductor integrated circuit device using four-terminal transistors 失效
标题翻译：半导体集成电路器件采用四端子晶体管
公开(公告)号：US07514728B2
公开(公告)日：2009-04-07
申请号：US11948350
申请日：2007-11-30
申请人： Takeshi Sugahara , Yasuhito Itaka
发明人： Takeshi Sugahara , Yasuhito Itaka
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L21/823892 , H01L27/0203 , H01L27/0928
摘要： In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.
摘要翻译：在第一导电类型的半导体衬底中，形成第一导电类型的第一阱区，第二导电类型的第二阱区和第二导电类型的第三阱区。除了形成第一阱区的区域之外，在半导体衬底中形成第二阱区。第三阱区域形成在半导体衬底中的第一阱区和第二阱区之下，使得第一阱区下面的第三阱区的一部分被去除，从而将第二阱区彼此电连接。

6. 发明授权

US07365377B2 Semiconductor integrated circuit device using four-terminal transistors 失效
标题翻译：半导体集成电路器件采用四端子晶体管
公开(公告)号：US07365377B2
公开(公告)日：2008-04-29
申请号：US11166243
申请日：2005-06-27
申请人： Takeshi Sugahara , Yasuhito Itaka
发明人： Takeshi Sugahara , Yasuhito Itaka
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L21/823892 , H01L27/0203 , H01L27/0928
摘要： In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.
摘要翻译：在第一导电类型的半导体衬底中，形成第一导电类型的第一阱区，第二导电类型的第二阱区和第二导电类型的第三阱区。除了形成第一阱区的区域之外，在半导体衬底中形成第二阱区。第三阱区域形成在半导体衬底中的第一阱区和第二阱区之下，使得第一阱区下面的第三阱区的一部分被去除，从而将第二阱区彼此电连接。

7. 发明申请

US20060197110A1 Semiconductor integrated circuit device using four-terminal transistors 失效
公开(公告)号：US20060197110A1
公开(公告)日：2006-09-07
申请号：US11166243
申请日：2005-06-27
申请人： Takeshi Sugahara , Yasuhito Itaka
发明人： Takeshi Sugahara , Yasuhito Itaka
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L21/823892 , H01L27/0203 , H01L27/0928
摘要： In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.

8. 发明申请

US20080073729A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING FOUR-TERMINAL TRANSISTORS 失效
标题翻译：使用四端子晶体管的半导体集成电路器件
公开(公告)号：US20080073729A1
公开(公告)日：2008-03-27
申请号：US11948350
申请日：2007-11-30
申请人： Takeshi SUGAHARA , Yasuhito Itaka
发明人： Takeshi SUGAHARA , Yasuhito Itaka
IPC分类号： H01L29/78
CPC分类号： H01L21/823892 , H01L27/0203 , H01L27/0928
摘要： In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.
摘要翻译：在第一导电类型的半导体衬底中，形成第一导电类型的第一阱区，第二导电类型的第二阱区和第二导电类型的第三阱区。除了形成第一阱区的区域之外，在半导体衬底中形成第二阱区。第三阱区域形成在半导体衬底中的第一阱区和第二阱区之下，使得第一阱区下面的第三阱区的一部分被去除，从而将第二阱区彼此电连接。

9. 发明授权

US06844926B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06844926B2
公开(公告)日：2005-01-18
申请号：US10205423
申请日：2002-07-26
申请人： Yasuhito Itaka
发明人： Yasuhito Itaka
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , G11C11/406 , G11C11/407 , G11C11/409 , G11C11/417 , H01L27/12 , G11C16/04
CPC分类号： H01L27/1203 , G11C7/065 , G11C7/12 , G11C11/417 , G11C2207/005
摘要： There is disclosed a semiconductor integrated circuit in which an equalize circuit is connected between input nodes N1, bN1 of a differential sense amplifier. A latch circuit is connected between nodes N2, bN2. A data change circuit is connected between the nodes N1 and bN2 and between the nodes bN1 and N2. A disconnection circuit is connected between the nodes N1 and N2 and between the nodes bN1 and bN2. In a state in which potentials of the input nodes N1, bN1 are equal to each other, the differential sense amplifier is operated, and output data of the amplifier is reversed by the data change circuit and subsequently latched by the latch circuit. The latched data is supplied to the input nodes N1, bN1 of the differential sense amplifier.
摘要翻译：公开了一种半导体集成电路，其中均衡电路连接在差分读出放大器的输入节点N1，bN1之间。节点N2，bN2之间连接锁存电路。数据变换电路连接在节点N1和bN2之间，节点bN1和N2之间。节点N1和N2之间以及节点bN1和bN2之间连接断开电路。在输入节点N1，bN1的电位彼此相等的状态下，差分读出放大器动作，放大器的输出数据由数据变换电路反转，随后由锁存电路锁存。锁存的数据被提供给差分读出放大器的输入节点N1，bN1。

10. 发明申请

US20060225013A1 Method of designing semiconductor integrated circuit and apparatus for designing the same 失效
标题翻译：设计半导体集成电路的方法及设计方法
公开(公告)号：US20060225013A1
公开(公告)日：2006-10-05
申请号：US11316744
申请日：2005-12-27
申请人： Yasuhito Itaka
发明人： Yasuhito Itaka
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether or not the voltage drop value exceeds a threshold value for each node, and inserts a buffer to a node determined that the voltage drop value exceeds the threshold value.
摘要翻译：一种设计具有多个晶体管的半导体集成电路的方法，计算与半导体集成电路中的每个节点处的栅极泄漏和沟道泄漏之和相对应的漏电流，估计由计算出的漏电流引起的电压降值，确定电压降值是否超过每个节点的阈值，并且将缓冲器插入到确定电压降值超过阈值的节点上。

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