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1. 发明申请

US20140085961A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140085961A1
公开(公告)日：2014-03-27
申请号：US14037547
申请日：2013-09-26
申请人： Kohji KANAMORI , Youngwoo PARK , Jintaek PARK , Kwang Soo SEOL , Jaeduk LEE
发明人： Kohji KANAMORI , Youngwoo PARK , Jintaek PARK , Kwang Soo SEOL , Jaeduk LEE
IPC分类号： G11C5/06 , G11C13/00
CPC分类号： G11C5/06 , G11C5/063 , G11C13/0002 , G11C13/0023 , G11C2213/73 , H01L27/222 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
摘要翻译：根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

2. 发明申请

US20150170714A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20150170714A1
公开(公告)日：2015-06-18
申请号：US14635588
申请日：2015-03-02
申请人： Jintaek PARK , Kohji KANAMORI , Youngwoo PARK , Jaeduk LEE
发明人： Jintaek PARK , Kohji KANAMORI , Youngwoo PARK , Jaeduk LEE
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C7/02 , G11C7/1039 , G11C7/18 , H01L27/11573 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.
摘要翻译：根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧，平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

3. 发明申请

US20140198552A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20140198552A1
公开(公告)日：2014-07-17
申请号：US14152440
申请日：2014-01-10
申请人： Jintaek PARK , Kohji KANAMORI , Youngwoo PARK , Jaeduk LEE
发明人： Jintaek PARK , Kohji KANAMORI , Youngwoo PARK , Jaeduk LEE
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C7/02 , G11C7/1039 , G11C7/18 , H01L27/11573 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.
摘要翻译：根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧，平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

4. 发明申请

US20170287928A1 SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20170287928A1
公开(公告)日：2017-10-05
申请号：US15430879
申请日：2017-02-13
申请人： Kohji KANAMORI , Shinhwan KANG , Kwang-Soo KIM , Youngwoo PARK , Chadong YEO , Jaegoo LEE
发明人： Kohji KANAMORI , Shinhwan KANG , Kwang-Soo KIM , Youngwoo PARK , Chadong YEO , Jaegoo LEE
IPC分类号： H01L27/11582 , H01L23/528 , G11C5/06 , H01L27/11565
CPC分类号： H01L27/11582 , G11C5/063 , H01L23/528 , H01L27/11565 , H01L27/1157
摘要： Semiconductor devices are provided. Semiconductor devices may include a stack structure including word lines stacked on a substrate, first vertical pillars and second vertical pillars that extend through the stack structure, a first string select line overlapping the first vertical pillars in a plan view, and a second string select line overlapping the second vertical pillars in the plan view and being spaced apart from the first string select line in a first direction. In a plan view, a shortest distance between a side of one of the first vertical pillars and a side of one of the second vertical pillars is less than a shortest distance between a side of the first string select line and a side of the second string select line.

5. 发明申请

US20130285006A1 VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20130285006A1
公开(公告)日：2013-10-31
申请号：US13742598
申请日：2013-01-16
申请人： Jintaek PARK , Youngwoo PARK , Jungdal CHOI
发明人： Jintaek PARK , Youngwoo PARK , Jungdal CHOI
IPC分类号： H01L45/00
CPC分类号： H01L45/1206 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1683
摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.
摘要翻译：可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线，沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。

6. 发明申请

US20150061155A1 Semiconductor Devices and Methods of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150061155A1
公开(公告)日：2015-03-05
申请号：US14469611
申请日：2014-08-27
申请人： YuJeong Seo , JinTaek PARK , Youngwoo PARK
发明人： YuJeong Seo , JinTaek PARK , Youngwoo PARK
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/02672 , H01L21/02532 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.
摘要翻译：本发明构思提供半导体器件及其制造方法。根据该方法，重复堆叠具有预定高度和活动孔的子堆叠结构。因此，可以改善电池分散，并且可以防止在蚀刻工艺中引起的各种误差，例如不开放的误差。作为通道使用的活性柱的粒径可以使用金属诱导横向结晶法增加或最大化，从而可提高电池电流。可以控制包括结晶诱导金属的金属硅化物层的形成位置，使得可以根据活性柱中的位置来控制结晶诱导金属的浓度等级。

7. 发明申请

US20130134377A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED RESISTIVE MEMORY CELLS 有权
标题翻译：具有三维电阻记忆细胞的半导体存储器件
公开(公告)号：US20130134377A1
公开(公告)日：2013-05-30
申请号：US13606789
申请日：2012-09-07
申请人： Jintaek PARK , Youngwoo PARK , Jungdal CHOI
发明人： Jintaek PARK , Youngwoo PARK , Jungdal CHOI
IPC分类号： H01L27/26 , H01L27/22
CPC分类号： H01L27/249 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.
摘要翻译：提供半导体存储器件。该装置可以包括彼此连接以构成选择线组的第一和第二选择线，顺序地堆叠在第一和第二选择线中的每一个上的多个字线，在第一和第二选择线之间排列成一行的垂直电极选择线，在选择线组的两侧中的每一侧排列成行的多个位线插头以及与字线交叉并将位线插头彼此连接的位线。

8. 发明申请

US20160343450A1 3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：三维半导体存储器件及其操作方法
公开(公告)号：US20160343450A1
公开(公告)日：2016-11-24
申请号：US15157720
申请日：2016-05-18
申请人： Changhyun LEE , Dohyun LEE , Youngwoo PARK , Su Jin AHN , Jaeduk LEE
发明人： Changhyun LEE , Dohyun LEE , Youngwoo PARK , Su Jin AHN , Jaeduk LEE
IPC分类号： G11C16/34 , G11C16/04 , H01L29/16 , H01L23/528 , H01L29/04 , G11C16/10 , H01L27/115
CPC分类号： H01L27/11524 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L27/11526 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/04 , H01L29/16
摘要： Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.
摘要翻译：公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号单元格阵列。电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案，第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。

9. 发明申请

US20180122695A1 SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 有权
公开(公告)号：US20180122695A1
公开(公告)日：2018-05-03
申请号：US15857961
申请日：2017-12-29
申请人： Dohyun LEE , Youngwoo PARK , Junghoon PARK , Jaeduk LEE
发明人： Dohyun LEE , Youngwoo PARK , Junghoon PARK , Jaeduk LEE
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/76816 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H01L23/53295 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

10. 发明申请

US20170040338A1 SEMICONDUCTOR MEMORY DEVICES HAVING CLOSELY SPACED BIT LINES 审中-公开
标题翻译：具有密闭空间位线的半导体存储器件
公开(公告)号：US20170040338A1
公开(公告)日：2017-02-09
申请号：US14989955
申请日：2016-01-07
申请人： Jaeduk LEE , Youngwoo PARK
发明人： Jaeduk LEE , Youngwoo PARK
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573
摘要： The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.
摘要翻译：本发明构思涉及半导体存储器件。半导体存储器件包括：基板，包括电路区域和分别设置在彼此相反的电路区域的两侧的第一和第二连接区域;逻辑结构，包括布置在电路区域上的逻辑电路和覆盖逻辑电路和逻辑结构上的存储器结构。逻辑电路包括与第一连接区域相邻设置的第一页缓冲器和与第二连接区域相邻设置的第二页缓冲器。存储器结构包括延伸到第一和第二连接区域中的至少一个的位线。

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