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1. 发明申请

US20090066613A1 DISPLAY APPARATUS 审中-公开
标题翻译：显示设备
公开(公告)号：US20090066613A1
公开(公告)日：2009-03-12
申请号：US11721140
申请日：2006-10-11
申请人： Kohichi Nakamura , Somei Kawasaki , Masami Iseki , Fujio Kawano
发明人： Kohichi Nakamura , Somei Kawasaki , Masami Iseki , Fujio Kawano
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G3/20 , G09G3/2096 , G09G3/3283 , G09G2300/0861 , G09G2310/0218 , G09G2310/0262 , G09G2310/027 , G09G2310/0272 , G09G2310/0297 , G09G2320/0233 , G09G2320/029 , G09G2320/0295 , G09G2320/043 , G09G2330/02
摘要： A display apparatus of the present invention has EL elements and pixel circuits 2 for supplying currents to the EL elements, which are arranged in a matrix fashion, and column control circuits 1 arranged corresponding to the number of columns of the matrix. The same number of column control circuits 1 and data lines 14 form a group, and the data line 14 which becomes an output of the column control circuit 1 is sequentially changed over in the group. Furthermore, the display apparatus includes means for correcting input signals among different groups. According to the present invention, even if a characteristic of the column control circuit 1 has a variation, no unevenness occurs in a displayed image.
摘要翻译：本发明的显示装置具有EL元件和用于向以矩阵方式布置的EL元件提供电流的像素电路2以及与矩阵列数相对应排列的列控制电路1。相同数量的列控制电路1和数据线14形成一组，并且在该组中顺序地改变成为列控制电路1的输出的数据线14。此外，显示装置包括用于校正不同组之间的输入信号的装置。根据本发明，即使列控制电路1的特性变化，也不会在显示图像中产生不均匀。

2. 发明授权

US08159482B2 Drive circuit, display apparatus using drive circuit, and evaluation method of drive circuit 有权
标题翻译：驱动电路，使用驱动电路的显示装置，以及驱动电路的评价方法
公开(公告)号：US08159482B2
公开(公告)日：2012-04-17
申请号：US12042477
申请日：2008-03-05
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3283 , G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2300/0861 , G09G2320/029 , G09G2320/043
摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.
摘要翻译：为了使驱动电路的输出精确，驱动电路由多个电流信号生成电路构成，用于向多个输出单元中的每一个输出电流信号，电流信号输出线，多个电流信号的输出通常连接发电电路，校正值输出电路，用于输出通过基于通过电流信号输出线输出的电流值来评估多个电流信号发生电路的一个或多个特定电路的输出而获得的校正值，以及校正电路，用于通过校正值校正提供给当前信号发生电路的图像信号。

3. 发明授权

US07903053B2 Current programming apparatus, matrix display apparatus and current programming method 有权
标题翻译：当前编程设备，矩阵显示设备和当前编程方法
公开(公告)号：US07903053B2
公开(公告)日：2011-03-08
申请号：US11275011
申请日：2005-12-01
申请人： Somei Kawasaki , Masami Iseki , Fujio Kawano , Takanori Yamashita
发明人： Somei Kawasaki , Masami Iseki , Fujio Kawano , Takanori Yamashita
IPC分类号： G09G3/30
CPC分类号： G09G3/3283 , G09G3/325 , G09G2300/0426 , G09G2300/0861 , G09G2310/0251 , G09G2320/0223
摘要： A matrix display apparatus includes a plurality of current-driven display devices arranged along row and column directions, a first circuit provided for each of the display devices, a plurality of data lines arranged for each column, with the data lines supplying an image data signal to a plurality of pixel circuits included in each one of the columns, and a plurality of row scanning lines for transmitting a scanning signal for selecting row by row the plurality of pixel circuits. The first circuit includes a field effect transistor for supplying one of the display devices with a current, which has a control electrode and two principal electrodes, a first switch connecting the control electrode and one of the principal electrodes of the field effect transistor, and a second switch having one terminal connected to the one of the principal electrodes of the field effect transistor and having another terminal connected to one of the data lines along the column of the first circuit. The first circuits in the column are connected in successively divided manner to the plurality of the data lines through the second switch.
摘要翻译：一种矩阵显示装置，包括沿着列和列方向排列的多个电流驱动显示装置，为每个显示装置设置的第一电路，为每列布置的多条数据线，数据线提供图像数据信号涉及包括在每列中的多个像素电路，以及多条行扫描线，用于发送用于逐行选择的多个像素电路的扫描信号。第一电路包括用于向显示装置中的一个提供电流的场效应晶体管，其具有控制电极和两个主电极，连接控制电极和场效应晶体管的主电极之一的第一开关，以及第二开关具有连接到场效应晶体管的一个主电极的一个端子，并且具有连接到沿着第一电路的列的数据线之一的另一端子。列中的第一电路通过第二开关以连续分割的方式连接到多条数据线。

4. 发明申请

US20080158112A1 Drive Circuit, Display Apparatus Using Drive Circuit, and Evaluation Method of Drive Circuit 失效
公开(公告)号：US20080158112A1
公开(公告)日：2008-07-03
申请号：US12042459
申请日：2008-03-05
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： G09G3/30
CPC分类号： G09G3/3283 , G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2300/0861 , G09G2320/029 , G09G2320/043
摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

5. 发明申请

US20080157828A1 Drive Circuit, Display Apparatus Using Drive Circuit, and Evaluation Method of Drive Circuit 有权
标题翻译：驱动电路，使用驱动电路的显示装置和驱动电路的评估方法
公开(公告)号：US20080157828A1
公开(公告)日：2008-07-03
申请号：US12042477
申请日：2008-03-05
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： H03B1/00
CPC分类号： G09G3/3283 , G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2300/0861 , G09G2320/029 , G09G2320/043
摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.
摘要翻译：为了使驱动电路的输出精确，驱动电路由多个电流信号生成电路构成，用于向多个输出单元中的每一个输出电流信号，电流信号输出线，多个电流信号的输出通常连接发电电路，校正值输出电路，用于输出通过基于通过电流信号输出线输出的电流值来评估多个电流信号发生电路的一个或多个特定电路的输出而获得的校正值，以及校正电路，用于通过校正值校正提供给当前信号发生电路的图像信号。

6. 发明授权

US06963615B2 Pixel modulation apparatus and method thereof 失效
标题翻译：像素调制装置及其方法
公开(公告)号：US06963615B2
公开(公告)日：2005-11-08
申请号：US10117204
申请日：2002-04-08
申请人： Somei Kawasaki , Masami Iseki , Hiroyuki Maru , Fujio Kawano
发明人： Somei Kawasaki , Masami Iseki , Hiroyuki Maru , Fujio Kawano
IPC分类号： B41J2/44 , H04N1/113 , H04N1/23 , H04N1/405 , H04N7/12
CPC分类号： H04N1/4056
摘要： A pixel modulation apparatus for converting pixel data D composed of N1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period T0. The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D1 expanded to N2 bits (N2>N1) at the period T0, a second data conversion unit which converts the pixel data D1 to pixel data D2 composed of N3/m bits at a period T0/m, a third data conversion unit which inputs n data from among the pixel data D2 and pixel data Dd2 constituting the pixel data D2 before having the period T0/m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D3 composed of N3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D3 to the pixel data signal composed of one bit at the period T0/m.
摘要翻译：一种像素调制装置，用于将由N 1位组成的像素数据D转换为由一位构成的像素数据信号。像素数据D在像素周期T 0被输入到装置中。该装置包括第一数据转换单元，其将像素数据D转换为在周期T 0处扩展为N 2位（N 2> N 1）的像素数据D 1，第二数据转换单元，将像素数据D 1转换为在周期T 0 / m处由N 3 / m位组成的像素数据D 2，第三数据转换单元，其在具有周期之前从像素数据D 2和构成像素数据D 2的像素数据Dd 2输入n个数据 T 0 / m以执行逻辑和运算，将预定数量（等于或小于n）次以将n个数据转换为由包括与预定数量相对应的附加数据的N 3位组成的像素数据D 3，以及第四数据转换单元，其将像素数据D 3转换为在周期T 0 / m处由一位组成的像素数据信号。

7. 发明授权

US08072542B2 Sampling device, display device using sampling device, and camera 有权
标题翻译：采样装置，使用采样装置的显示装置和相机
公开(公告)号：US08072542B2
公开(公告)日：2011-12-06
申请号：US11693291
申请日：2007-03-29
申请人： Masami Iseki , Somei Kawasaki , Fujio Kawano
发明人： Masami Iseki , Somei Kawasaki , Fujio Kawano
IPC分类号： H03L7/00
CPC分类号： H04N5/23293 , G09G3/006 , G09G3/3241 , G09G3/3283 , G09G2320/0233 , G09G2320/029 , H04N5/14
摘要： A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.
摘要翻译：校正采样信号发生电路设置在多级采样信号产生电路之后，用于响应于输入定时信号顺序产生采样信号，扩展采样电路设置在用于对视频信号进行采样的多级采样电路之后在采样信号的定时，并且在由扩展采样电路产生的采样信号的定时对数据信号进行采样。在定时调整期间，产生用于调整的数据信号，数据信号和定时信号的相位相对偏移，采样电路的输出通过各个开关提供给公共输出线，并且相位基于公共输出线的输出确定最佳定时信号或视频信号。

8. 发明申请

US20070229692A1 SAMPLING DEVICE, DISPLAY DEVICE USING SAMPLING DEVICE, AND CAMERA 有权
标题翻译：采样设备，使用采样设备的显示设备和摄像机
公开(公告)号：US20070229692A1
公开(公告)日：2007-10-04
申请号：US11693291
申请日：2007-03-29
申请人： Masami ISEKI , Somei Kawasaki , Fujio Kawano
发明人： Masami ISEKI , Somei Kawasaki , Fujio Kawano
IPC分类号： H04N3/14
CPC分类号： H04N5/23293 , G09G3/006 , G09G3/3241 , G09G3/3283 , G09G2320/0233 , G09G2320/029 , H04N5/14
摘要： A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit of sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit of sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.
摘要翻译：校正采样信号产生电路设置在响应于输入定时信号顺序产生采样信号的多级采样信号产生电路之后，扩展采样电路设置在对视频信号进行采样的多级采样电路之后在采样信号的定时，并且在由扩展采样电路产生的采样信号的定时对数据信号进行采样。在定时调整期间，产生用于调整的数据信号，数据信号和定时信号的相位相对偏移，采样电路的输出通过各个开关提供给公共输出线，并且相位基于公共输出线的输出确定最佳定时信号或视频信号。

9. 发明申请

US20050122150A1 Driver, display and recorder 有权
标题翻译：驱动程序，显示和录像机
公开(公告)号：US20050122150A1
公开(公告)日：2005-06-09
申请号：US10994310
申请日：2004-11-23
申请人： Masami Iseki , Somei Kawasaki , Fujio Kawano , Takanori Yamashita
发明人： Masami Iseki , Somei Kawasaki , Fujio Kawano , Takanori Yamashita
IPC分类号： G09G3/30 , G09F9/30 , G09G3/20 , G09G3/32 , H03K5/153
CPC分类号： G09G3/3283 , G09G3/3241 , G09G3/325 , G09G3/3266 , G09G2300/0842 , G09G2300/0861 , G09G2310/0289 , G09G2330/021 , G09G2330/026 , G09G2330/045
摘要： The present application discloses a driver having a configuration comprising: a drive transistor for supplying a current of the quantity corresponding to a gate potential, into the element as a driving current; a first switch installed in the path of the driving current passing between the element and the drive transistor, for controlling the flow of the driving current; a second switch for switching between the first state of setting the gate potential of the drive transistor and the second state of keeping the set gate potential; a circuit for supplying a signal for controlling the flow of the driving current in a restricted state to the first switch, for a predetermined period in a period after the starting the supply of the potential for driving the drive transistor from a power source and until start of driving the element in a normal operation; a circuit for supplying a signal for setting the second switch at the first state, to the second switch: and a circuit for interrupting a signal for setting the gate potential while the second switch is in the first state in the predetermined period.
摘要翻译：本申请公开了一种驱动器，其具有如下结构：驱动晶体管，用于将与栅极电位相对应的量的电流作为驱动电流提供到元件中; 安装在通过元件和驱动晶体管之间的驱动电流的路径中的第一开关，用于控制驱动电流的流动; 第二开关，用于在设置驱动晶体管的栅极电位的第一状态和保持所设置的栅极电位的第二状态之间切换; 在开始从电源驱动驱动晶体管的电位开始到起动之间的期间内，将预定时间段提供用于将限制状态下的驱动电流的流动控制到第一开关的电路在正常操作中驱动元件; 用于向第二开关提供用于将第二开关设置的信号的电路提供给第二开关;以及用于在第二开关处于预定周期中处于第一状态时中断用于设置栅极电位的信号的电路。

10. 发明授权

US08154539B2 Drive circuit, display apparatus using drive circuit, and evaluation method of drive circuit 失效
公开(公告)号：US08154539B2
公开(公告)日：2012-04-10
申请号：US12042459
申请日：2008-03-05
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3283 , G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2300/0861 , G09G2320/029 , G09G2320/043
摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

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