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1. 发明授权

US07394090B2 Non-volatile memory and the fabrication method 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07394090B2
公开(公告)日：2008-07-01
申请号：US11798364
申请日：2007-05-14
申请人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
发明人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C14/009 , H01L27/1104 , H01L27/24 , H01L45/04 , H01L45/145
摘要： A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.
摘要翻译：一种非易失性存储器，包括：第一基板（100）和第二基板（110），所述第一基板（100）具有布置成矩阵的多个开关元件（4），并且多个第一电极（18）被连接至所述开关元件（4），所述第二基板（110）具有导电膜（32）以及其电阻值通过施加电脉冲而改变的记录层（34），其中所述多个第一电极（18）为由记录层（34）整体覆盖，记录层（34）由此保持在多个第一电极（18）和导电膜（32）之间; 所述第一基板（100）还包括第二电极（22），所述第二电极（22）电连接到所述导电膜（32），其电压保持在设定电平，同时向所述记录层施加电流（ 34）。这种非易失性存储器以低成本实现高集成度。

2. 发明申请

US20070210362A1 Non-volatile memory and the fabrication method 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20070210362A1
公开(公告)日：2007-09-13
申请号：US11798364
申请日：2007-05-14
申请人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
发明人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
IPC分类号： H01L27/11
CPC分类号： G11C13/0004 , G11C14/009 , H01L27/1104 , H01L27/24 , H01L45/04 , H01L45/145
摘要： A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.
摘要翻译：一种非易失性存储器，包括：第一基板（100）和第二基板（110），所述第一基板（100）具有布置成矩阵的多个开关元件（4），并且多个第一电极（18）被连接至所述开关元件（4），所述第二基板（110）具有导电膜（32）以及其电阻值通过施加电脉冲而改变的记录层（34），其中所述多个第一电极（18）为由记录层（34）整体覆盖，记录层（34）由此保持在多个第一电极（18）和导电膜（32）之间; 所述第一基板（100）还包括第二电极（22），所述第二电极（22）电连接到所述导电膜（32），其电压保持在设定电平，同时向所述记录层施加电流（ 34）。这种非易失性存储器以低成本实现高集成度。

3. 发明申请

US20050093043A1 Non-volatile memory and the fabrication method 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20050093043A1
公开(公告)日：2005-05-05
申请号：US10980309
申请日：2004-11-04
申请人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
发明人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
IPC分类号： G11C16/02 , H01L27/11 , H01L27/24 , H01L45/00 , H01L29/76 , H01L21/48
CPC分类号： G11C13/0004 , G11C14/009 , H01L27/1104 , H01L27/24 , H01L45/04 , H01L45/145
摘要： A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.
摘要翻译：一种非易失性存储器，包括：第一基板（100）和第二基板（110），所述第一基板（100）具有布置成矩阵的多个开关元件（4），并且多个第一电极（18）被连接至所述开关元件（4），所述第二基板（110）具有导电膜（32）以及其电阻值通过施加电脉冲而改变的记录层（34），其中所述多个第一电极（18）为由记录层（34）整体覆盖，记录层（34）由此保持在多个第一电极（18）和导电膜（32）之间; 所述第一基板（100）还包括第二电极（22），所述第二电极（22）电连接到所述导电膜（32），其电压保持在设定电平，同时向所述记录层施加电流（ 34）。这种非易失性存储器以低成本实现高集成度。

4. 发明授权

US07232703B2 Non-volatile memory and the fabrication method 有权
公开(公告)号：US07232703B2
公开(公告)日：2007-06-19
申请号：US10980309
申请日：2004-11-04
申请人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
发明人： Kiyoyuki Morita , Noboru Yamada , Akihito Miyamoto , Takashi Ohtsuka , Hideyuki Tanaka
IPC分类号： H01L21/06
CPC分类号： G11C13/0004 , G11C14/009 , H01L27/1104 , H01L27/24 , H01L45/04 , H01L45/145
摘要： A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34).This non-volatile memory achieves high integration at low cost.

5. 发明授权

US07291857B2 Non-volatile memory 失效
标题翻译：非易失性存储器
公开(公告)号：US07291857B2
公开(公告)日：2007-11-06
申请号：US10967222
申请日：2004-10-19
申请人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
发明人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
IPC分类号： H01L47/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1625
摘要： A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.
摘要翻译：一种非易失性存储器（1），其包括绝缘基板（11），所述绝缘基板具有从所述基板的前表面延伸穿过其延伸到其后表面的多个第一电极（15），形成在一个表面上的第二电极基板（11）的一侧，以及保持在第一电极（15）和第二电极（12）之间的记录层（14），并且通过施加在第一电极（15）和第二电极（12），所述多个第一电极（15）在构成单个存储单元（MC）的区域中与记录层（14）电连接。非易失性存储器（1）可以降低功耗，并具有很大的设计自由度和高可靠性。

6. 发明申请

US20050045864A1 Non-volatile memory 失效
标题翻译：非易失性存储器
公开(公告)号：US20050045864A1
公开(公告)日：2005-03-03
申请号：US10967222
申请日：2004-10-19
申请人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
发明人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
IPC分类号： H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1625
摘要： A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.
摘要翻译：一种非易失性存储器（1），其包括绝缘基板（11），所述绝缘基板具有从所述基板的前表面延伸穿过其延伸到其后表面的多个第一电极（15），形成在一个表面上的第二电极基板（11）的一侧，以及保持在第一电极（15）和第二电极（12）之间的记录层（14），并且通过施加在第一电极（15）和第二电极（12），所述多个第一电极（15）在构成单个存储单元（MC）的区域中与记录层（14）电连接。非易失性存储器（1）可以降低功耗，并具有很大的设计自由度和高可靠性。

7. 发明授权

US06844564B2 Non-volatile memory 失效
公开(公告)号：US06844564B2
公开(公告)日：2005-01-18
申请号：US10608130
申请日：2003-06-30
申请人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
发明人： Hideyuki Tanaka , Takashi Ohtsuka , Kiyoyuki Morita , Kiyoshi Morimoto
IPC分类号： H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1625
摘要： A non-volatile memory (1) which comprises an insulating substrate (11) having a plurality of first electrodes (15) extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode (12) formed on one surface side of the substrate (11), and a recording layer (14) held between the first electrodes (15) and the second electrode (12) and variable in resistance value by electric pulses applied across the first electrodes (15) and the second electrode (12), the plurality of first electrodes (15) being electrically connected to the recording layer (14) in a region constituting a single memory cell (MC). The non-volatile memory (1) can be reduced in power consumption and has great freedom of design and high reliability.

8. 发明授权

US07023014B2 Non-volatile memory and fabrication method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07023014B2
公开(公告)日：2006-04-04
申请号：US10716621
申请日：2003-11-20
申请人： Kiyoshi Morimoto , Hideyuki Tanaka , Takashi Ohtsuka , Akihito Miyamoto
发明人： Kiyoshi Morimoto , Hideyuki Tanaka , Takashi Ohtsuka , Akihito Miyamoto
IPC分类号： H01L29/18
CPC分类号： G11C13/0004 , H01L27/0814 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144 , H01L45/1625 , H01L45/1666 , H01L45/1675
摘要： The present invention relates to a non-volatile memory comprising: a first electrode (11); a second electrode (12); and a phase-change recording medium (14) sandwiched between the first electrode (11) and the second electrode (12), in which resistance value is varied by applying an electrical pulse across the first electrode (11) and the second electrode (12), at least one of the first electrode (11) and the second electrode (12) contains as a main ingredient at least one member selected from the group consisting of ruthenium, rhodium and osmium, and the phase-change recording medium (14) is formed of a phase-change material that contains chalcogen(s). This non-volatile memory exhibits improved durability and reliability by preventing deterioration of property (i.e., mutual impurity diffusion between the electrode and the phase-change recording medium) caused by application of current.
摘要翻译：本发明涉及一种非易失性存储器，包括：第一电极（11）; 第二电极（12）; 以及夹在第一电极（11）和第二电极（12）之间的相变记录介质（14），其中通过在第一电极（11）和第二电极（12）上施加电脉冲来改变电阻值），第一电极（11）和第二电极（12）中的至少一个包含选自钌，铑和锇中的至少一种元素和相变记录介质（14）作为主要成分，由含有硫族元素的相变材料形成。这种非易失性存储器通过防止由施加电流引起的性能劣化（即，电极和相变记录介质之间的相互杂质扩散）而显示出改进的耐久性和可靠性。

9. 发明授权

US06949780B2 Semiconductor device 有权
公开(公告)号：US06949780B2
公开(公告)日：2005-09-27
申请号：US10847323
申请日：2004-05-18
申请人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
发明人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
IPC分类号： H01L27/10 , G11C27/00 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C27/005 , G11C11/54 , H01L2924/0002 , H01L2924/00
摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

10. 发明授权

US06940740B2 Multilevel semiconductor memory device and method for driving the same as a neuron element in a neural network computer 有权
标题翻译：多电平半导体存储器件及其在神经网络计算机中作为神经元元件驱动的方法
公开(公告)号：US06940740B2
公开(公告)日：2005-09-06
申请号：US10428840
申请日：2003-05-05
申请人： Michihito Ueda , Takashi Ohtsuka , Kiyoyuki Morita
发明人： Michihito Ueda , Takashi Ohtsuka , Kiyoyuki Morita
IPC分类号： G11C11/22 , G11C11/56 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/223 , G11C11/54 , G11C11/5657 , H01L27/105 , H01L27/11507 , H01L29/7881
摘要： A semiconductor device includes: a control-voltage supply unit 110; an MOS transistor including a gate electrode 109 and drain and source regions 103a and 103b; a dielectric capacitor 104; and a resistor 106. The dielectric capacitor 104 and the resistor 106 are disposed in parallel and interposed between the gate electrode 109 and the control-voltage supply unit 110. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitor 104 and the gate electrode 109 upon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.
摘要翻译：半导体器件包括：控制电压提供单元110; 包括栅电极109和漏极和源极区103a和103b的MOS晶体管; 介质电容器104; 和电阻器106。介质电容器104和电阻器106并联设置并插入在栅电极109和控制电压供给单元110之间。利用这种结构，在施加电压时，介质电容器104和栅电极109的中间电极中的每一个中积累电荷，从而改变MOS晶体管的阈值。以这种方式，可以将输入信号的历史存储为MOS晶体管中的漏极电流的变化，从而允许保持多电平信息。

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