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    • 3. 发明授权
    • Data processing apparatus and DMA data transfer method
    • 数据处理设备和DMA数据传输方式
    • US06708234B2
    • 2004-03-16
    • US09964464
    • 2001-09-28
    • Kiyotaka MotekiNorio MichiieYasuhiro HattoriHiromitsu ShimizuTakao Okamura
    • Kiyotaka MotekiNorio MichiieYasuhiro HattoriHiromitsu ShimizuTakao Okamura
    • G06F1328
    • G06F13/28
    • In a data processing apparatus, an image memory has a descriptor region and an image region, the image region storing a plurality of blocks of image data, the descriptor region storing a corresponding number of descriptor information blocks for the plurality of image data blocks. A DMA controller controls DMA data transfer of the image data blocks from the image region according to each descriptor information block in the descriptor region. The DMA controller comprises a register which stores one of the descriptor information blocks from the descriptor region of the image memory, and a control unit which determines, at a time of occurrence of a CPU interrupt, a start timing of a DMA data output operation of the DMA controller during a DMA data input operation of the DMA controller when an image editing request contained in input image data is received, the CPU interrupt being caused to occur by an interrupt request bit of the descriptor information block read from the register.
    • 在数据处理装置中,图像存储器具有描述符区域和图像区域,所述图像区域存储多个图像数据块,所述描述符区域存储用于所述多个图像数据块的相应数量的描述符信息块。 DMA控制器根据描述符区域中的每个描述符信息块来控制来自图像区域的图像数据块的DMA数据传输。 DMA控制器包括存储来自图像存储器的描述符区域的描述符信息块之一的寄存器,以及控制单元,其在执行CPU中断时确定DMA数据输出操作的开始定时 当接收到包含在输入图像数据中的图像编辑请求时DMA DMA控制器的DMA数据输入操作期间的DMA控制器,由从寄存器读取的描述符信息块的中断请求位引起CPU中断。