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1. 发明申请

US20130254454A1 MEMORY SYSTEM AND BANK INTERLEAVING METHOD 有权
公开(公告)号：US20130254454A1
公开(公告)日：2013-09-26
申请号：US13600578
申请日：2012-08-31
申请人： Takashi IDE , Kiyotaka IWASAKI , Kouji WATANABE , Hiroyuki NANJOU , Makoto MORIYA
发明人： Takashi IDE , Kiyotaka IWASAKI , Kouji WATANABE , Hiroyuki NANJOU , Makoto MORIYA
IPC分类号： G06F12/06
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F12/0246 , G06F12/0607 , G06F13/14 , G06F13/18 , G06F2212/7208
摘要： According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.

2. 发明申请

US20120192032A1 DATA STORAGE APPARATUS, MEMORY CONTROL APPARATUS AND METHOD FOR CONTROLLING FLASH MEMORIES 失效
标题翻译：数据存储装置，存储器控制装置和控制闪速存储器的方法
公开(公告)号：US20120192032A1
公开(公告)日：2012-07-26
申请号：US13301335
申请日：2011-11-21
申请人： Kiyotaka IWASAKI
发明人： Kiyotaka IWASAKI
IPC分类号： G11C29/00 , G06F11/16
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a data storage apparatus includes a channel controller, an error correction controller, and an additional correction module. The channel controller is configured to control writing to and reading from the nonvolatile memories of respective channels. The error correction controller is configured to use inter-channel error correction codes during any read process, performing inter-channel correction process on those of the data items read under the control of the channel controller, which have been designated. The additional correction module is configured to designate, in accordance with errors detected by the channel controller, data items to additionally correct, and to notify the data items so designated to the error correction controller while the channel controller is reading the data necessary in the inter-channel correction process.
摘要翻译：根据一个实施例，数据存储装置包括信道控制器，纠错控制器和附加校正模块。通道控制器被配置为控制对各个通道的非易失性存储器的写入和读取。错误校正控制器被配置为在任何读取处理期间使用信道间纠错码，对已经指定的信道控制器的控制下读取的数据项执行信道间校正处理。附加校正模块被配置为根据由信道控制器检测到的错误来指定数据项以附加地校正，并且在信道控制器正在读取在相互之间必需的数据时将如此指定的数据项通知给纠错控制器通道校正过程。

3. 发明申请

US20140040695A1 STORAGE APPARATUS AND CONTROLLER 有权
标题翻译：存储设备和控制器
公开(公告)号：US20140040695A1
公开(公告)日：2014-02-06
申请号：US13691063
申请日：2012-11-30
申请人： Kiyotaka IWASAKI
发明人： Kiyotaka IWASAKI
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , G06F11/1008 , G06F11/1012
摘要： According to at least one embodiment, a storage apparatus reads first sector data and a first error correcting code. The storage apparatus performs first decoding for the read first sector data using the read first error correcting code. The storage apparatus stores an error correction result by the first decoding. The storage apparatus performs second decoding for decoding-data associated with a second error correcting code using the second error correcting code. The storage apparatus transfers the second error correcting code and the decoding-data via the first buffer storing the error correction result.
摘要翻译：根据至少一个实施例，存储装置读取第一扇区数据和第一纠错码。存储装置使用读取的第一纠错码对读取的第一扇区数据执行第一解码。存储装置通过第一解码存储纠错结果。存储装置使用第二纠错码对与第二纠错码相关联的数据进行解码的第二解码。存储装置经由存储误差校正结果的第一缓冲器来传送第二纠错码和解码数据。

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