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1. 发明授权

US08483000B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08483000B2
公开(公告)日：2013-07-09
申请号：US13587047
申请日：2012-08-16
申请人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
发明人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
IPC分类号： G11C7/02 , G11C7/10 , G11C8/00
CPC分类号： G11C8/16
摘要： The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.
摘要翻译：本发明旨在提供一种具有双端口存储电路的半导体器件，其中复制单元的放置对芯片面积增大的影响减小。双端口存储器电路的存储单元阵列具有：第一复制单元阵列，用于响应来自双端口之一的读操作指令; 以及用于响应来自另一个双端口的读取操作的指令的第二复制单元阵列。每个复制单元阵列具有：通过相互短路的并行线获得的复制位线，所述并行线具有通过将数据输入/输出的互补位线的反转位线和非反相位线切割一半而获得的长度存储器单元的端子耦合; 以及耦合到复制位线并且具有与存储器单元相当的晶体管放置的复制单元。

2. 发明申请

US20120307551A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120307551A1
公开(公告)日：2012-12-06
申请号：US13587047
申请日：2012-08-16
申请人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
发明人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C8/16
摘要： The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has : a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has : replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.
摘要翻译：本发明旨在提供一种具有双端口存储电路的半导体器件，其中复制单元的放置对芯片面积增大的影响减小。双端口存储器电路的存储单元阵列具有：第一复制单元阵列，用于响应来自双端口之一的读操作指令; 以及用于响应来自另一个双端口的读取操作的指令的第二复制单元阵列。每个复制单元阵列具有：通过相互短路的并行线获得的复制位线，所述并行线具有通过将数据输入/输出的互补位线的反转位线和非反相位线切割一半而获得的长度存储器单元的端子耦合; 以及耦合到复制位线并且具有与存储器单元相当的晶体管放置的复制单元。

3. 发明授权

US08259524B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08259524B2
公开(公告)日：2012-09-04
申请号：US12838466
申请日：2010-07-18
申请人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
发明人： Kiyotada Funane , Yuta Yanagitani , Shinji Tanaka
IPC分类号： G11C7/10 , G11C7/02 , G11C8/00
CPC分类号： G11C8/16
摘要： The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.
摘要翻译：本发明旨在提供一种具有双端口存储电路的半导体器件，其中复制单元的放置对芯片面积增大的影响减小。双端口存储器电路的存储单元阵列具有：第一复制单元阵列，用于响应来自双端口之一的读操作指令; 以及用于响应来自另一个双端口的读取操作的指令的第二复制单元阵列。每个复制单元阵列具有：通过相互短路的并行线获得的复制位线，所述并行线具有通过将数据输入/输出的互补位线的反转位线和非反相位线切割一半而获得的长度存储器单元的端子耦合; 以及耦合到复制位线并且具有与存储器单元相当的晶体管放置的复制单元。

4. 发明申请

US20110032751A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110032751A1
公开(公告)日：2011-02-10
申请号：US12838466
申请日：2010-07-18
申请人： Kiyotada FUNANE , Yuta Yanagitani , Shinji Tanaka
发明人： Kiyotada FUNANE , Yuta Yanagitani , Shinji Tanaka
IPC分类号： G11C11/00 , G11C8/16
CPC分类号： G11C8/16
摘要： The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.
摘要翻译：本发明旨在提供一种具有双端口存储电路的半导体器件，其中复制单元的放置对芯片面积增大的影响减小。双端口存储器电路的存储单元阵列具有：第一复制单元阵列，用于响应来自双端口之一的读操作指令; 以及用于响应来自另一个双端口的读取操作的指令的第二复制单元阵列。每个复制单元阵列具有：通过相互短路的并行线获得的复制位线，所述并行线具有通过将数据输入/输出的互补位线的反转位线和非反相位线切割一半而获得的长度存储器单元的端子耦合; 以及耦合到复制位线并且具有与存储器单元相当的晶体管放置的复制单元。

5. 发明授权

US09245614B2 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US09245614B2
公开(公告)日：2016-01-26
申请号：US14234479
申请日：2011-07-29
申请人： Ken Shibata , Yuta Yanagitani
发明人： Ken Shibata , Yuta Yanagitani
IPC分类号： G11C5/06 , G11C11/412 , H01L27/02 , H01L27/11 , H01L21/8238 , H01L27/092 , G11C5/14 , G11C11/417 , G11C11/419
CPC分类号： H01L27/1104 , G11C5/14 , G11C11/412 , G11C11/417 , G11C11/418 , G11C11/419 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/1116 , H01L29/0684 , H01L29/0847 , H01L29/1079 , H01L29/42356
摘要： A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

6. 发明申请

US20140177312A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20140177312A1
公开(公告)日：2014-06-26
申请号：US14234479
申请日：2011-07-29
申请人： Ken Shibata , Yuta Yanagitani
发明人： Ken Shibata , Yuta Yanagitani
IPC分类号： H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C5/14 , G11C11/412 , G11C11/417 , G11C11/418 , G11C11/419 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/1116 , H01L29/0684 , H01L29/0847 , H01L29/1079 , H01L29/42356
摘要： A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.
摘要翻译：具有高自由度布置的半导体器件具有第一部分AR1，其中多个p型阱PW和n型阱NW沿着X轴方向交替布置成彼此相邻。多个井PW的公共供电区域（ARP2）布置在一侧，以将AR1插入Y轴方向，并且用于多个井NW的公共供电区域（ARN2）布置在另一边。在PW阱的供电区域（ARP2）中，形成具有沿X轴方向延伸的细长形状的p +型供电扩散层P +（DFW）。在AR1中布置有沿X轴方向延伸以跨越PW和NW阱之间的边界的多个栅极层GT，并且相应地形成多个MIS晶体管。

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