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1. 发明授权

US4425646A Input data synchronizing circuit 失效
标题翻译：输入数据同步电路
公开(公告)号：US4425646A
公开(公告)日：1984-01-10
申请号：US281492
申请日：1981-07-08
申请人： Kiyoshi Kinoshita , Takatoshi Ishii
发明人： Kiyoshi Kinoshita , Takatoshi Ishii
IPC分类号： G06F3/06 , G11B5/016 , G11B19/28 , G11B20/14 , G11B27/10 , H03L7/00 , H04L7/033
CPC分类号： G06F3/0601 , G11B19/28 , G11B20/1403 , G11B20/1419 , G11B27/10 , G11B5/016 , G06F2003/0692 , G11B2220/2512
摘要： An input data synchronizing circuit of the invention has a synchronous control counter. Part of count value of the synchronous control counter is supplied to a count register. The count register accesses a parameter ROM utilizing, as part of an address, a count value (phase status) during the input of current data and a count value (phase status) during input of immediately preceding data. The parameter ROM outputs a correction value as an initial value for the synchronous control counter so that the synchronous control counter would output a WINDOW signal synchronous with the input data near the center of the pulse width of the WINDOW signal. The circuit of the invention further includes a rotation correction register which holds stationary time shift information serially input by the rotational errors of the floppy disk drives and which outputs the information to the parameter ROM as part of the address.
摘要翻译：本发明的输入数据同步电路具有同步控制计数器。同步控制计数器的计数值的一部分被提供给计数寄存器。作为地址的一部分，计数寄存器使用在输入当前数据期间的计数值（相位状态）和在紧接在前的数据的输入期间的计数值（相位状态）来访问参数ROM。参数ROM输出作为同步控制计数器的初始值的校正值，使得同步控制计数器将输出与WINDOW信号的脉冲宽度中心附近的输入数据同步的WINDOW信号。本发明的电路还包括旋转校正寄存器，其保持由软盘驱动器的旋转错误串行输入的固定时间偏移信息，并将该信息作为地址的一部分输出到参数ROM。

2. 发明申请

US20120218283A1 Method for Obtaining Brighter Images from an LED Projector 审中-公开
标题翻译：从LED投影机获取更亮的图像的方法
公开(公告)号：US20120218283A1
公开(公告)日：2012-08-30
申请号：US13037078
申请日：2011-02-28
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G5/02
CPC分类号： H04N9/3182 , H04N9/3111 , H04N9/3164
摘要： A method for improving brightness of projected images from an LED projector employing a plurality of LEDs of different colors by determining, from a histogram of a frame of an image to be projected, an effective maximum saturation. A plurality of main channels and a plurality of subchannels are created, one main channel and at least one subchannel for each color LED. Then the amplitude of the main channel and a subchannel for each color are determined based upon the effective maximum saturation of the frame of the image, followed by using the main channel and the at least one subchannel for a color to drive an LED of that color to generate the image.
摘要翻译：一种用于通过从要投影的图像的帧的直方图确定有效的最大饱和度来改善来自使用多种不同颜色的LED的LED投影仪的投影图像的亮度的方法。创建多个主通道和多个子通道，一个主通道和用于每个颜色LED的至少一个子通道。然后，基于图像的帧的有效最大饱和度确定用于每种颜色的主通道和子通道的幅度，然后使用主通道和至少一个子通道来驱动该颜色的LED 生成图像。

3. 发明申请

US20080068396A1 Gamma Uniformity Correction Method and System 审中-公开
标题翻译：伽马均匀校正方法与系统
公开(公告)号：US20080068396A1
公开(公告)日：2008-03-20
申请号：US11533309
申请日：2006-09-19
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G5/02
CPC分类号： G09G3/3611 , G09G3/2055 , G09G3/3648 , G09G2320/0233 , G09G2320/0238 , G09G2320/0276 , G09G2320/0285 , G09G2340/02
摘要： A method and system are provided for performing gamma correction on display data. Aspects the exemplary embodiment include using at least a portion of the display data to fetch in parallel from a table memory a gamma correction data value stored at an odd address and a gamma correction data value stored at an even address; detecting when the display data comprises a low address; and in response to detecting that the display data comprises a low address, performing a right shift on the gamma correction data values, thereby decreasing the values of the gamma correction data prior to performing interpolation on the gamma compensation data values.
摘要翻译：提供了一种用于对显示数据执行伽马校正的方法和系统。方面，示例性实施例包括使用显示数据的至少一部分从表存储器并行获取存储在偶数地址处的伽马校正数据值和存储在偶数地址处的伽马校正数据值; 检测显示数据何时包括低地址; 并且响应于检测到显示数据包括低地址，对伽马校正数据值执行右移，从而在对伽马补偿数据值执行内插之前减少伽马校正数据的值。

4. 发明授权

US06680738B1 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator 有权
标题翻译：单块虚拟帧缓冲区转换为多块物理块，用于多块显示刷新生成器
公开(公告)号：US06680738B1
公开(公告)日：2004-01-20
申请号：US09683852
申请日：2002-02-22
申请人： Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
发明人： Takatoshi Ishii , Edmund Cheung , Sherwood Brannon
IPC分类号： G06F1210
CPC分类号： G09G5/39 , G09G5/14 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2330/021
摘要： A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
摘要翻译：与电池供电设备一起使用的片上系统（SOC）图形控制器允许降低功耗的显示模式。微处理器写入作为虚拟存储器中单个连续地址块的帧缓冲器。存储器管理单元（MMU）将帧缓冲器地址转换为多个物理块。图形控制器从多个物理块中获取像素，包括片上存储器中的块和外部存储器中的块。在低功耗模式下，像素只能从较低功耗的片上存储器中取出，而不是较高功率的外部存储器。定义一个较小的显示窗口，窗口外的像素将被虚拟数据替代，从而消除外部存储器提取。较小的显示窗口落在片内存储器的第一个块内。在待机模式下，状态和其他信息可以显示在较小的显示窗口中，全屏显示全功能模式。

5. 发明授权

US06362834B1 Flat-panel display controller with improved dithering and frame rate control 有权
公开(公告)号：US06362834B1
公开(公告)日：2002-03-26
申请号：US09430999
申请日：1999-11-01
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G510
摘要： A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

6. 发明授权

US4804948A Video display control system 失效
标题翻译：视频显示控制系统
公开(公告)号：US4804948A
公开(公告)日：1989-02-14
申请号：US77984
申请日：1987-07-27
申请人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
发明人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
IPC分类号： G06F3/153 , G06T11/00 , G09G5/02 , G09G1/16
CPC分类号： G09G5/026
摘要： A video display control system displays a video image composed of a plurality of display elements on a screen of a video display unit. The system comprises a memory (VRAM) for storing a plurality of color codes each representing at least one display element and a video display controller (VDP). The VDP comprises a mode register for selecting one of normal display and transparency processing modes, display processing circuit for reading the color codes from the VRAM, a backdrop color register for storing a color code such as one representing a backdrop color, a detection circuit for detecting a predetermined color code from the color codes read by the display processing circuit, and a selector controlled by an output of the detection circuit. In the normal display mode, the selector outputs all color codes read by the display processing circuit to the display unit. In the transparency processing mode, the selector outputs the color codes read by the display processing circuit to the display unit when the predetermined color code is not detected, and outputs the color code contained in the backdrop color register to the display unit when the predetermined color code is detected. The VDP further comprises another detection circuit for detecting a second predetermined color code from the color codes outputted from the selector to output a control signal. And if the second predetermined color code is detected in the transparency processing mode, the display unit displays an image in accordance with an external video signal.
摘要翻译：视频显示控制系统在视频显示单元的屏幕上显示由多个显示元件组成的视频图像。该系统包括用于存储代表至少一个显示元件和视频显示控制器（VDP）的多个颜色代码的存储器（VRAM）。 VDP包括用于选择正常显示和透明度处理模式之一的模式寄存器，用于从VRAM读取颜色代码的显示处理电路，用于存储诸如表示背景颜色的颜色代码的颜色代码的背景颜色寄存器，用于从由显示处理电路读取的颜色代码检测预定的颜色代码，以及由检测电路的输出控制的选择器。在正常显示模式下，选择器将由显示处理电路读出的所有颜色代码输出到显示单元。在透明度处理模式中，当未检测到预定颜色代码时，选择器将由显示处理电路读取的颜色代码输出到显示单元，并且当预定颜色在显示单元中输出包含在背景颜色寄存器中的颜色代码检测到代码。 VDP还包括用于从从选择器输出的颜色代码中检测第二预定颜色代码以输出控制信号的另一个检测电路。并且如果在透明度处理模式中检测到第二预定颜色代码，则显示单元根据外部视频信号显示图像。

7. 发明授权

US4789854A Color video display apparatus 失效
标题翻译：彩色视频显示装置
公开(公告)号：US4789854A
公开(公告)日：1988-12-06
申请号：US526
申请日：1987-01-05
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G1/28 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/14 , G09G5/30
CPC分类号： G09G5/026 , G09G5/06
摘要： A color video display apparatus displays a first image represented by luminance and color difference data stored in a VRAM and a second image represented by color codes stored in the same VRAM on a screen of a CRT display unit in a superimposed relation. Each address of the VRAM stores the luminance data and an attribute bit of the corresponding display dot of the first image, and the color difference data is formed with respect to each group of a predetermined number of display dots of the first image and stored in a predetermined number of addresses of the VRAM. The color code of each dot of the second image is stored in the corresponding addresses of the VRAM. The data sequentially read from the addresses of the VRAM are shifted into a register group composed of a predetermined number of registers. Data contained in specific bits of the registers is transferred to another register each time the predetermined number of data are read from the VRAM, and is outputted from the another register as the color difference data. When the attribute bit contained in specific one of the registers of the register group is "0", color data representative of a color of the corresponding display dot is formed from the luminance data contained in the specific register and the color difference data contained in the another register. On the other hand, when the attribute bit contained in the specific register is "1", the color data is formed by a look-up table from the color code contained in the specific register.
摘要翻译：彩色视频显示装置以叠加的关系在CRT显示单元的屏幕上显示由存储在VRAM中的亮度和色差数据表示的第一图像和存储在相同VRAM中的颜色代码表示的第二图像。 VRAM的每个地址存储亮度数据和第一图像的相应显示点的属性位，并且对于第一图像的预定数量的显示点的每一组形成色差数据，并存储在预定数量的VRAM的地址。第二图像的每个点的颜色代码存储在VRAM的相应地址中。从VRAM的地址顺序读取的数据被移位到由预定数量的寄存器组成的寄存器组中。每当从VRAM读取预定数量的数据时，寄存器的特定位中包含的数据被传送到另一个寄存器，并从另一个寄存器输出作为色差数据。当包含在寄存器组的特定寄存器组中的属性位为“0”时，表示相应显示点的颜色的颜色数据由包含在特定寄存器中的亮度数据和包含在特定寄存器中的色差数据形成另一个登记册。另一方面，当特定寄存器中包含的属性位为“1”时，由包含在特定寄存器中的颜色代码由查找表形成彩色数据。

8. 发明授权

US4751502A Display controller for displaying a cursor on either of a CRT display device or a liquid crystal display device 失效
标题翻译：用于在CRT显示装置或液晶显示装置中的任一个上显示光标的显示控制器
公开(公告)号：US4751502A
公开(公告)日：1988-06-14
申请号：US844159
申请日：1986-03-26
申请人： Takatoshi Ishii , Makoto Kaneko
发明人： Takatoshi Ishii , Makoto Kaneko
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00 , G09G5/08 , G09G1/00
CPC分类号： G09G3/3644 , G09G3/3611 , G09G5/08
摘要： A display controller which can display a cursor on either of a CRT display or a liquid crystal type display device is described. The liquid crystal type display device is a type that has an upper and lower display blocks which are scanned substantially in parallel. This display controller allows the display position of the cursor to be designated in the same manner, independent of the type of display device used. The display controller operates in a time sharing manner, alternately on the upper and lower display blocks of the liquid crystal device. Two groups of data corresponding to these upper and lower blocks are formed and are supplied to the liquid crystal display device substantially in parallel. X and Y coordinate positions of the cursor position are also stored. The cursor pattern signal for the liquid crystal display device is also stored in a time shared manner.
摘要翻译：描述可以在CRT显示器或液晶型显示装置中的任何一个上显示光标的显示控制器。液晶型显示装置是具有大致平行扫描的上下显示块的种类。该显示控制器允许以相同的方式指定光标的显示位置，而与所使用的显示装置的类型无关。显示控制器以分时方式操作，交替地在液晶装置的上部和下部显示块上操作。形成与这些上下块对应的两组数据，并且基本并行地供给到液晶显示装置。也存储光标位置的X和Y坐标位置。用于液晶显示装置的光标图形信号也以时间共享的方式存储。

9. 发明授权

US4720803A Display control apparatus for performing multicolor display by tiling display 失效
标题翻译：用于通过平铺显示进行多色显示的显示控制装置
公开(公告)号：US4720803A
公开(公告)日：1988-01-19
申请号：US850086
申请日：1986-04-09
申请人： Takatoshi Ishii
发明人： Takatoshi Ishii
IPC分类号： G09G1/28 , G06F15/40 , G09G1/14
CPC分类号： G09G1/285
摘要： A display control apparatus has a memory for storing luminance data corresponding to a plurality of color elements for color display, the luminance data being used as display data of dots to be displayed at a raster scan type display unit, a circuit for reading out the luminance data corresponding to the respective color elements of given dots for dot display at the display unit, and a video signal converter for enabling/disabling at least one-dot display intervals a binary video signal which is to be transmitted to the display unit and corresponds to a color element when specific luminance data of this color element read out from the memory by the readout circuit has a given level for an interval corresponding to at least two dots along a raster direction, and for transmitting the luminance data to the display unit in accordance with the enable/disabled state of the binary video signal.
摘要翻译：显示控制装置具有用于存储对应于用于彩色显示的多个色彩元素的亮度数据的存储器，亮度数据被用作要在光栅扫描型显示单元上显示的点的显示数据，读出亮度的电路对应于在显示单元处用于点显示的给定点的各个色彩元素的数据，以及视频信号转换器，用于使至少一点显示间隔能够/禁用要发送到显示单元的二进制视频信号并对应于当由读出电路从存储器读出的该色素的特定亮度数据具有对应于沿着光栅方向的至少两个点的间隔的给定电平时的颜色元素，并且用于根据光栅方向将亮度数据发送到显示单元具有二进制视频信号的使能/禁止状态。

10. 发明授权

US4660070A Video display processor 失效
标题翻译：视频显示处理器
公开(公告)号：US4660070A
公开(公告)日：1987-04-21
申请号：US736828
申请日：1985-05-22
申请人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
发明人： Kazuhiko Nishi , Takatoshi Ishii , Ryozo Yamashita , Shigemitsu Yamaoka , Takatoshi Okumura
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/00 , G09G5/02 , G09G5/12 , G09G5/393 , H04N5/44
CPC分类号： G09G5/393 , G09G5/02 , G09G5/12
摘要： A video display processor (VDP) for use with a central processing unit, a video RAM (VRAM) and a video display unit is capable of writing video image data supplied from an external video device such as a television set into the VRAM. The VDP comprises a first input terminal for receiving the external video image data and a second input terminal for receiving horizontal and vertical synchronization signals from the external video device. The VDP generates address data in accordance with the horizontal and vertical synchronization signals and supplies the address data to the VRAM when processing of the external video image data is designated. The VDP also supplies the received external video image data to the VRAM thereby to write the external video image data into addresses of the VRAM designated by the address data. The external video image data may be either color codes representative of colors of display elements of a video image displayed at the external video device or data representative of amplitude levels of an analog video signal outputted from the external video device.
摘要翻译：与中央处理单元，视频RAM（VRAM）和视频显示单元一起使用的视频显示处理器（VDP）能够将从诸如电视机的外部视频设备提供的视频图像数据写入到VRAM中。 VDP包括用于接收外部视频图像数据的第一输入端子和用于从外部视频装置接收水平和垂直同步信号的第二输入端子。 VDP根据水平和垂直同步信号产生地址数据，并且在指定外部视频图像数据的处理时将地址数据提供给VRAM。 VDP还将接收到的外部视频图像数据提供给VRAM，从而将外部视频图像数据写入由地址数据指定的VRAM的地址。外部视频图像数据可以是表示在外部视频设备上显示的视频图像的显示元素的颜色的颜色代码或表示从外部视频设备输出的模拟视频信号的幅度电平的数据。

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