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1. 发明授权

US5479703A Method of making a printed circuit board or card 失效
标题翻译：制作印刷电路板或卡片的方法
公开(公告)号：US5479703A
公开(公告)日：1996-01-02
申请号：US309777
申请日：1994-09-21
申请人： Kishor V. Desai , Harold Kohn , Richard C. Senger , Donald P. Seraphim
发明人： Kishor V. Desai , Harold Kohn , Richard C. Senger , Donald P. Seraphim
IPC分类号： B42D15/10 , G06K19/077 , H01L21/48 , H01L23/538 , H05K3/20 , H05K3/28 , H05K3/32 , H05K3/40 , H05K3/42 , H05K3/46 , H05K3/34
CPC分类号： H05K3/462 , H01L21/4853 , H01L21/4857 , H01L23/5384 , H01L23/5385 , H01L2224/16225 , H01L2224/16235 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H05K2201/09536 , H05K2201/09563 , H05K2201/096 , H05K2201/10234 , H05K2203/0338 , H05K2203/0376 , H05K2203/063 , H05K3/20 , H05K3/205 , H05K3/28 , H05K3/328 , H05K3/4046 , H05K3/423 , H05K3/4623 , Y10S428/901 , Y10T29/49126 , Y10T29/49144 , Y10T29/49149 , Y10T29/49165
摘要： A multi-layer printed circuit board or card including a plurality of circuitized power cores, the circuitized power cores include a layer of an electrically conductive material having a layer of electrically insulating material attached on both sides thereof. The circuitized power cores also include a plurality of plated through holes formed therethrough in substantially the same pattern on each circuitized power core. The circuitized power cores are parallel to each other such that corresponding plated through holes in the two circuitized power cores are co-linear. A plurality of substantially spherical balls are located between the circuitized power cores and are in contact with the corresponding plated through holes on facing cards. The balls have a diameter slightly larger than the opening of the plated through holes and are made of an electrically conductive material.
摘要翻译：一种多层印刷电路板或卡片，包括多个电路化的电源核心，电路化的电源核心包括一层导电材料，其上具有一层电绝缘材料，该电绝缘材料层在其两侧。电路化的功率核心还包括在每个电路化的功率核心上以基本上相同的图案形成的多个电镀通孔。电路化的功率核心彼此平行，使得两个电路化的功率核心中相应的电镀通孔是共线的。多个基本上球形的球位于电路化的功率核之间并且与相对的卡上的对应的电镀通孔接触。球的直径略大于电镀通孔的开口，并且由导电材料制成。

2. 发明授权

US5170931A Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate 失效
公开(公告)号：US5170931A
公开(公告)日：1992-12-15
申请号：US644528
申请日：1991-01-23
申请人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
发明人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
IPC分类号： H01L21/98 , H01L23/498 , H01L23/538 , H05K1/14 , H05K3/34 , H05K3/36
CPC分类号： H01L25/50 , H01L23/4985 , H01L23/5385 , H05K3/3478 , H05K3/363 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2924/01014 , H01L2924/01079 , H01L2924/01322 , H01L2924/15321 , H05K1/141 , H05K2201/0215 , H05K2201/049 , H05K2201/10234 , H05K2201/10477 , H05K2201/10681 , H05K2201/10734 , H05K2201/10984 , H05K2203/0165 , H05K2203/0278 , H05K2203/041 , H05K2203/0557
摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template having a pattern of openings corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.

3. 发明授权

US5201451A Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate 失效
标题翻译：用于将柔性膜半导体芯片载体安装在电路化基板上的方法和装置
公开(公告)号：US5201451A
公开(公告)日：1993-04-13
申请号：US727047
申请日：1991-07-09
申请人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Endwell , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
发明人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Endwell , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
IPC分类号： H01L21/98 , H01L23/498 , H01L23/538 , H05K1/14 , H05K3/34 , H05K3/36
CPC分类号： H01L25/50 , H01L23/4985 , H01L23/5385 , H05K3/3478 , H05K3/363 , H01L2224/16 , H01L2224/73253 , H01L2924/01014 , H01L2924/01079 , H01L2924/01322 , H05K1/141 , H05K2201/0215 , H05K2201/049 , H05K2201/10234 , H05K2201/10477 , H05K2201/10681 , H05K2201/10734 , H05K2201/10984 , H05K2203/0165 , H05K2203/0278 , H05K2203/041 , H05K2203/0557
摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled,; leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.
摘要翻译：公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。然后，将该组件加热以回流间隔件的焊料，并拆卸组装夹具。留下安装在第二级电子封装上的柔性膜半导体芯片载体，其中载体的柔性膜具有所需的平面几何形状。

4. 发明授权

US5199879A Electrical assembly with flexible circuit 失效
标题翻译：电气组装与柔性电路
公开(公告)号：US5199879A
公开(公告)日：1993-04-06
申请号：US840212
申请日：1992-02-24
申请人： Harold Kohn , Kishor V. Desai , Ronald J. Romanosky , George J. Saxenmeyer, Jr. , Reinhold E. Tomek , James R. Webb
发明人： Harold Kohn , Kishor V. Desai , Ronald J. Romanosky , George J. Saxenmeyer, Jr. , Reinhold E. Tomek , James R. Webb
IPC分类号： H05K1/14 , H01R12/58 , H01R24/58 , H05K1/11 , H05K3/00 , H05K3/30 , H05K3/32 , H05K3/46
CPC分类号： H01R24/58 , H05K3/326 , H01R2103/00 , H05K1/118 , H05K2201/091 , H05K2201/09809 , H05K2201/1059 , H05K2201/10704 , H05K3/306 , H05K3/4691
摘要： An electrical assembly which includes a first circuit member (e.g., TCM) with at least one conductive pin projecting therefrom for being frictionally and electrically engaged by a flexible portion of circuit means of a second circuit member (e.g., PCB). An opening is provided within the PCB relative to the flexible portions such that these portions project at least partly across the opening and frictionally engage respective conductive portions of the pin when inserted within the opening. Each of these flexible portions in turn is part of a circuit layer which may be coupled to respective conductive planes or the like within the PCB, while the respective conductive portions of the pin may in turn be electrically coupled to various conductive layers within/upon the TCM.
摘要翻译：一种电气组件，其包括具有从其突出的至少一个导电针的第一电路构件（例如TCM），用于由第二电路构件（例如PCB）的电路装置的柔性部分摩擦和电接合。在PCB内相对于柔性部分设置开口，使得这些部分至少部分地突出穿过开口并且当插入到开口内时摩擦地接合销的相应导电部分。这些柔性部分中的每一个又是电路层的一部分，其可以耦合到PCB内的相应的导电平面等，而引脚的相应导电部分又可以电连接到/ 中医。

5. 发明授权

US5159535A Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate 失效
标题翻译：用于将柔性膜半导体芯片载体安装在电路化基板上的方法和装置
公开(公告)号：US5159535A
公开(公告)日：1992-10-27
申请号：US365326
申请日：1989-06-13
申请人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
发明人： Kishor V. Desai , Nelson P. Franchak , Robert H. Katyl , Harold Kohn , Tamar A. Sholtes , Vilakkudi G. Veeraraghavan , Charles G. Woychik
IPC分类号： H01L21/98 , H01L23/498 , H01L23/538 , H05K1/14 , H05K3/34 , H05K3/36
CPC分类号： H01L25/50 , H01L23/4985 , H01L23/5385 , H05K3/3478 , H05K3/363 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2924/01014 , H01L2924/01079 , H01L2924/01322 , H01L2924/15321 , H05K1/141 , H05K2201/0215 , H05K2201/049 , H05K2201/10234 , H05K2201/10477 , H05K2201/10681 , H05K2201/10734 , H05K2201/10984 , H05K2203/0165 , H05K2203/0278 , H05K2203/041 , H05K2203/0557
摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template having a pattern of openings corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.
摘要翻译：公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。然后，将该组件加热以回流间隔件的焊料，并且组装夹具被拆卸，使得柔性膜半导体芯片载体安装在第二层电子封装上，其中载体的柔性膜根据需要具有平面几何形状。可以使用具有对应于柔性膜半导体芯片载体上的外引线接合焊盘的图案的开口图案的特殊模板将间隔件附接到柔性膜半导体芯片载体。

6. 发明授权

US08772946B2 Reduced stress TSV and interposer structures 有权
标题翻译：减少应力TSV和插入结构
公开(公告)号：US08772946B2
公开(公告)日：2014-07-08
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

7. 发明申请

US20130328186A1 REDUCED STRESS TSV AND INTERPOSER STRUCTURES 有权
标题翻译：减少应力TSV和间接结构
公开(公告)号：US20130328186A1
公开(公告)日：2013-12-12
申请号：US13492064
申请日：2012-06-08
申请人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
发明人： Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/48 , H01L21/28 , H01L23/498
CPC分类号： H01L23/34 , H01L21/76841 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05558 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/1134 , H01L2224/1147 , H01L2224/13082 , H01L2224/13083 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13565 , H01L2224/32105 , H01L2924/00011 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81805
摘要： A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
摘要翻译：部件可以包括在基板的开口内延伸的基板和导电通孔。基底可以具有第一和第二相对表面。开口可以从第一表面延伸到第二表面，并且可以具有远离第一表面延伸的内壁。电介质材料可以在内壁暴露。导电通孔可以在邻近第一表面的开口内限定释放通道。释放通道可以具有在与第一表面平行且在五微米以内的平面的方向上离内壁的第一距离内的边缘，第一距离是最小宽度的一微米和百分之五的最小宽度在飞机上开了边缘可以沿着内壁延伸以跨越内壁的圆周的至少百分之五。

8. 发明授权

US07727781B2 Manufacture of devices including solder bumps 有权
标题翻译：制造包括焊料凸点的器件
公开(公告)号：US07727781B2
公开(公告)日：2010-06-01
申请号：US12220182
申请日：2008-07-22
申请人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
发明人： Joze Eura Antol , Kishor V. Desai , John William Osenbach , Brian Thomas Vaccaro
IPC分类号： G01L31/26 , H01L21/66
CPC分类号： H05K3/3452 , H05K3/3457 , H05K2201/099 , H05K2203/0271 , H05K2203/162
摘要： Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.
摘要翻译：焊接接头（例如印刷电路板焊盘处的接头）的典型测试尚未被证明完全可以预测这种接头的最终性能。已经发现，这种缺乏可靠性至少部分地是由于这些焊盘在测试期间失去与下面的衬底的粘附或分层的倾向。相比之下，这种情况并不是典型的设备使用期间引起的现象。为了消除这种不可靠性的原因，测试结构与制造设备批次一起进行。使用相同的焊盘处理，并且焊盘尺寸在测试结构中大大扩大。测试结构用于预测批次中的设备的性能，然后相应地处理批次。

9. 发明授权

US06552266B2 High performance chip packaging and method 有权
公开(公告)号：US06552266B2
公开(公告)日：2003-04-22
申请号：US09770913
申请日：2001-01-26
申请人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
发明人： Timothy F. Carden , Glenn O. Dearing , Kishor V. Desai , Stephen R. Engle , Randall Stutzman , George H. Thiel
IPC分类号： H01L2302
CPC分类号： H01L23/10 , H01L21/50 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49169
摘要： A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

10. 发明授权

US06266249B1 Semiconductor flip chip ball grid array package 有权
标题翻译：半导体倒装芯片球栅阵列封装
公开(公告)号：US06266249B1
公开(公告)日：2001-07-24
申请号：US09375835
申请日：1999-08-16
申请人： Kishor V. Desai , Sunil Patel , Ramaswamy Ranganathan
发明人： Kishor V. Desai , Sunil Patel , Ramaswamy Ranganathan
IPC分类号： H05K118
CPC分类号： H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.
摘要翻译：存在半导体封装以及相关方法。该封装包括具有顶表面和底表面的衬底，该衬底具有从衬底的顶表面延伸到衬底的底表面的多个导电通孔。具有活性表面的半导体器件，具有多个接合焊盘的活性表面通过与通孔对准的基底孔的粘合剂附着到基底上。通孔也与焊盘对准。焊料用于将每个焊盘与相应的通孔电连接和机械耦合。每个通孔又连接到形成在基底的底部上的焊球。

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