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1. 发明授权

US08357579B2 Methods of forming integrated circuits 有权
标题翻译：形成集成电路的方法
公开(公告)号：US08357579B2
公开(公告)日：2013-01-22
申请号：US13042539
申请日：2011-03-08
申请人： King-Yuen Wong , Ming-Lung Cheng , Chien-Tai Chan , Da-Wen Lin , Chung-Cheng Wu
发明人： King-Yuen Wong , Ming-Lung Cheng , Chien-Tai Chan , Da-Wen Lin , Chung-Cheng Wu
IPC分类号： H01L21/335 , H01L21/336 , H01L29/76 , H01L21/02
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/165 , H01L29/66636 , H01L29/7834
摘要： A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.
摘要翻译：形成集成电路的方法包括在衬底上形成栅极结构。去除基板的一部分以形成与栅极结构相邻的凹部。在每个凹部的侧壁和底部形成有具有第一类型掺杂剂的富掺杂层。在每个凹部中形成含硅材料结构。含硅材料结构具有第二种掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

2. 发明申请

US20110248322A1 Piezoelectric Gate-Induced Strain 审中-公开
标题翻译：压电门诱导应变
公开(公告)号：US20110248322A1
公开(公告)日：2011-10-13
申请号：US12758568
申请日：2010-04-12
申请人： King-Yuen Wong , Chien-Tai Chan , Da-Wen Lin , Chung-Cheng Wu
发明人： King-Yuen Wong , Chien-Tai Chan , Da-Wen Lin , Chung-Cheng Wu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/513 , H01L29/517 , H01L29/78 , H01L29/7843
摘要： An embodiment is a semiconductor device. The semiconductor device comprises a substrate, an electrode over the substrate, and a piezoelectric layer disposed between the substrate and the electrode. The piezoelectric layer causes a strain in the substrate when an electric field is generated by the electrode.
摘要翻译：一个实施例是半导体器件。半导体器件包括衬底，衬底上的电极以及设置在衬底和电极之间的压电层。当电极产生电场时，压电层在衬底中引起应变。

3. 发明授权

US08759943B2 Transistor having notched fin structure and method of making the same 有权
标题翻译：具有切口鳍结构的晶体管及其制造方法
公开(公告)号：US08759943B2
公开(公告)日：2014-06-24
申请号：US12900626
申请日：2010-10-08
申请人： Chih-Hung Tseng , Da-Wen Lin , Chien-Tai Chan , Chia-Pin Lin , Li-Wen Weng , An-Shen Chang , Chung-Cheng Wu
发明人： Chih-Hung Tseng , Da-Wen Lin , Chien-Tai Chan , Chia-Pin Lin , Li-Wen Weng , An-Shen Chang , Chung-Cheng Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7853
摘要： A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).
摘要翻译：晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

4. 发明申请

US20130062670A1 Device with Engineered Epitaxial Region and Methods of Making Same 有权
标题翻译：具有工程外延区域的设备及其制造方法
公开(公告)号：US20130062670A1
公开(公告)日：2013-03-14
申请号：US13232738
申请日：2011-09-14
申请人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
发明人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L29/045 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.
摘要翻译：工程外延区域通过提供阻挡层来补偿MOS器件的短沟道效应，以减少或防止掺杂剂扩散，同时减少或消除阻挡层的副作用，例如增加BJT器件的漏电流和/ 或降低整流器的击穿电压。这些副作用通过阻挡层和衬底之间的非共形掺杂剂富集层降低或消除，这降低了结的突然性，从而降低了接合区的电场。这种方案对于片上系统应用是特别有利的，其中期望在通常的工艺步骤的同时制造MOS，BJT和整流器件。

5. 发明授权

US09117843B2 Device with engineered epitaxial region and methods of making same 有权
标题翻译：具有工程外延区域的器件及其制造方法
公开(公告)号：US09117843B2
公开(公告)日：2015-08-25
申请号：US13232738
申请日：2011-09-14
申请人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
发明人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8238 , H01L21/8249 , H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L29/045 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.
摘要翻译：工程外延区域通过提供阻挡层来补偿MOS器件的短沟道效应，以减少或防止掺杂剂扩散，同时减少或消除阻挡层的副作用，例如增加BJT器件的漏电流和/ 或降低整流器的击穿电压。这些副作用通过阻挡层和衬底之间的非共形掺杂剂富集层降低或消除，这降低了结的突然性，从而降低了接合区的电场。这种方案对于片上系统应用是特别有利的，其中期望在通常的工艺步骤的同时制造MOS，BJT和整流器件。

6. 发明授权

US08921946B2 Integrated circuit resistor 有权
标题翻译：集成电路电阻
公开(公告)号：US08921946B2
公开(公告)日：2014-12-30
申请号：US13294251
申请日：2011-11-11
申请人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L29/772 , H01L21/265 , H01L27/06 , H01L29/8605 , H01L29/66
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
摘要翻译：半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。触点设置在电阻上。还提供了一种制造这种半导体器件的方法。

7. 发明申请

US20130119480A1 INTEGRATED CIRCUIT RESISTOR 有权
标题翻译：集成电路电阻
公开(公告)号：US20130119480A1
公开(公告)日：2013-05-16
申请号：US13294251
申请日：2011-11-11
申请人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L29/772 , H01L21/02 , H01L29/02
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
摘要翻译：半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。触点设置在电阻上。还提供了一种制造这种半导体器件的方法。

8. 发明授权

US07994016B2 Method for obtaining quality ultra-shallow doped regions and device having same 有权
标题翻译：用于获得优质超浅掺杂区域的方法及其装置
公开(公告)号：US07994016B2
公开(公告)日：2011-08-09
申请号：US12616406
申请日：2009-11-11
申请人： Chun-Hsiung Tsai , Chun-Feng Nieh , Da-Wen Lin , Chien-Tai Chan
发明人： Chun-Hsiung Tsai , Chun-Feng Nieh , Da-Wen Lin , Chien-Tai Chan
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.
摘要翻译：在衬底的表面中形成PMOS晶体管的超浅p型轻掺杂漏极（LDD）区域的方法包括以下步骤：提供惰性气体，含硼源和任选的碳的气态混合物其中气态混合物的浓度与惰性气体和任选的含碳源（如果存在）一起稀释至少99.5％，将气态混合物形成等离子体，并形成LDD区域，其中形成步骤包括使用等离子体将硼等离子体掺杂到衬底中。在LDD区域下方并与LDD区域相邻的衬底中形成N型口袋区域，其中对于阈值电压为100mV的PMOS晶体管，n型袋区域包括掺杂剂浓度小于6.0×1018的磷杂质原子/ cm 3或低/高阈值电压的比例较低/较高掺杂剂浓度。

9. 发明申请

US20110127610A1 Multiple-Gate Semiconductor Device and Method 有权
标题翻译：多栅极半导体器件及方法
公开(公告)号：US20110127610A1
公开(公告)日：2011-06-02
申请号：US12797382
申请日：2010-06-09
申请人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
发明人： Tung Ying Lee , Li-Wen Weng , Chien-Tai Chan , Da-Wen Lin , Hsien-Chin Lin
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/823431 , H01L27/0886 , H01L29/785
摘要： A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
摘要翻译：公开了一种用于制造多栅极半导体器件的系统和方法。一个实施例包括多个散热片，其中散热片内隔离区域延伸到小于鳍间隔离区域的衬底内。去除未被栅极堆叠覆盖的多个鳍片的区域，并且从衬底形成源极/漏极区域，以避免在源极/漏极区域中的鳍片之间形成空隙。

10. 发明授权

US08785286B2 Techniques for FinFET doping 有权
标题翻译： FinFET掺杂技术
公开(公告)号：US08785286B2
公开(公告)日：2014-07-22
申请号：US12702803
申请日：2010-02-09
申请人： Chun Hsiung Tsai , Chien-Tai Chan , Mao-Rong Yeh , Da-Wen Lin
发明人： Chun Hsiung Tsai , Chien-Tai Chan , Mao-Rong Yeh , Da-Wen Lin
IPC分类号： H01L21/336 , H01L21/26 , H01L21/42 , H01L21/223
CPC分类号： H01L29/66803 , H01L21/2236 , H01L21/2254 , H01L21/26526 , H01L21/26586
摘要： A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
摘要翻译：一种形成集成电路的方法包括提供半导体晶片，该半导体晶片包括在半导体晶片的表面上分配的半导体鳍; 在所述半导体鳍片的顶表面和侧壁上形成具有杂质的富掺杂层，其中所述杂质为n型或p型; 执行敲击植入以将杂质驱动到半导体鳍片中; 并除去富含掺杂剂的层。

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