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1. 发明申请

US20120195354A1 Serial Protocol for Agile Sample Rate Switching 有权
标题翻译：用于敏捷采样率切换的串行协议
公开(公告)号：US20120195354A1
公开(公告)日：2012-08-02
申请号：US13444928
申请日：2012-04-12
申请人： King-Hon Lau , Johannes G. Ransijn , Harold T. Simmonds , James D. Yoder
发明人： King-Hon Lau , Johannes G. Ransijn , Harold T. Simmonds , James D. Yoder
IPC分类号： H04B1/38
CPC分类号： H04M3/005 , H04L5/1423 , H04L25/0266
摘要： The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
摘要翻译：本发明提供一种通信协议和串行接口，其具有近似固定的接口时钟并且能够适应各种通信速率。接口采用可扩展或缩小的可变长度帧，以获得期望的通信速率，即使接口时钟速率保持近似恒定。本发明还提供了一种用于设计敏捷屏障界面的方法。特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。然后可以通过将屏障时钟速率除以EA速率来获得对应于每个通信速率的帧长度。最后，本发明提供了能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷障碍。

2. 发明授权

US08761236B2 Serial protocol for agile sample rate switching 有权
标题翻译：用于敏捷采样率切换的串行协议
公开(公告)号：US08761236B2
公开(公告)日：2014-06-24
申请号：US13444928
申请日：2012-04-12
申请人： King-Hon Lau , Johannes G. Ransijn , Harold T. Simmonds , James D. Yoder
发明人： King-Hon Lau , Johannes G. Ransijn , Harold T. Simmonds , James D. Yoder
IPC分类号： H04B1/38
CPC分类号： H04M3/005 , H04L5/1423 , H04L25/0266
摘要： The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
摘要翻译：本发明提供一种通信协议和串行接口，其具有近似固定的接口时钟并且能够适应各种通信速率。接口采用可扩展或缩小的可变长度帧，以获得期望的通信速率，即使接口时钟速率保持近似恒定。本发明还提供了一种用于设计敏捷屏障界面的方法。特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。然后可以通过将屏障时钟速率除以＆Sgr＆amp; Dgr来获得对应于每个通信速率的帧长度; 率。最后，本发明提供了能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷障碍。

3. 发明授权

US08213489B2 Serial protocol for agile sample rate switching 有权
标题翻译：用于敏捷采样率切换的串行协议
公开(公告)号：US08213489B2
公开(公告)日：2012-07-03
申请号：US11206314
申请日：2005-08-17
申请人： King-Hon Lau , Johannes G. Ransijn , Harold Thomas Simmonds , James D Yoder
发明人： King-Hon Lau , Johannes G. Ransijn , Harold Thomas Simmonds , James D Yoder
IPC分类号： H04B1/38
CPC分类号： H04M3/005 , H04L5/1423 , H04L25/0266
摘要： The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.
摘要翻译：本发明提供一种通信协议和串行接口，其具有近似固定的接口时钟并且能够适应各种通信速率。接口采用可扩展或缩小的可变长度帧，以获得期望的通信速率，即使接口时钟速率保持近似恒定。本发明还提供了一种用于设计敏捷屏障界面的方法。特别地，屏障时钟速率优选地被选择为屏障接口必须处理的各种通信速率的近似公倍数。然后可以通过将屏障时钟速率除以＆Sgr＆amp; Dgr来获得对应于每个通信速率的帧长度; 率。最后，本发明提供了能够以各种数据速率和大致固定的接口时钟速率通过串行接口传送数据的敏捷障碍。

4. 发明授权

US07773733B2 Single-transformer digital isolation barrier 有权
标题翻译：单变压器数字隔离屏障
公开(公告)号：US07773733B2
公开(公告)日：2010-08-10
申请号：US11159614
申请日：2005-06-23
申请人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H04M11/00
CPC分类号： H04M19/001
摘要： The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
摘要翻译：本发明提供了一种在DAA中的系统侧和线路侧电路之间的单个数字通信链路，能够承载数据信号并将大量电力传送到线路侧电路。本发明包括系统侧接口电路，线路侧接口电路和包括变压器的隔离屏障。每个接口电路能够连接到上游通信电路（线路侧或系统侧），从而可以接收要跨越隔离屏障传输到另一个接口电路的数据信号，并且其可以传递数据跨隔离屏障的信号与另一个接口电路接收。线路侧接口电路还可以包括整流器和存储装置。

5. 发明授权

US07969335B2 Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters 有权
标题翻译：数字校正多位delta-sigma数模转换器的非线性误差
公开(公告)号：US07969335B2
公开(公告)日：2011-06-28
申请号：US12041204
申请日：2008-03-03
申请人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译：提供了用于误差反馈DAC的多位ADAC非线性的数字校正。通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。然后，INL值用于补偿ADAC在数字域中的失真。当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。

6. 发明授权

US07362247B2 Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters 有权
标题翻译：数字校正多位delta-sigma数模转换器的非线性误差
公开(公告)号：US07362247B2
公开(公告)日：2008-04-22
申请号：US11430285
申请日：2006-05-08
申请人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus Arias , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译：提供了用于误差反馈DAC的多位ADAC非线性的数字校正。通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。然后，INL值用于补偿ADAC在数字域中的失真。当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。

7. 发明申请

US20100246695A1 SIGNAL-POWERED INTEGRATED CIRCUIT WITH ESD PROTECTION 有权
标题翻译：具有ESD保护功能的信号集成电路
公开(公告)号：US20100246695A1
公开(公告)日：2010-09-30
申请号：US12794845
申请日：2010-06-07
申请人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H04B3/00
CPC分类号： H04M19/001
摘要： The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.
摘要翻译：本发明提供一种信号供电的集成电路（IC）。 IC包括集成电路管芯，其包括接地节点，供电节点和用于接收具有数据内容和预定能量的数字数据信号的第一终端。形成在集成电路管芯上的接收缓冲器连接到第一终端并且能够接收与数字数据信号相关联的数据内容。整流器也形成在集成电路管芯上。整流器包括连接在第一端子和接地节点之间的第一二极管和连接在第一端子与供电节点之间的第二二极管。整流器被配置为对数字数据信号进行整流，并将数字数据信号的至少一部分预定能量传递给供电节点。第一和第二二极管中的每一个能够承受ESD冲击。

8. 发明申请

US20080150773A1 DIGITAL CORRECTION OF NONLINEARITY ERRORS OF MULTIBIT DELTA-SIGMA DIGITAL TO ANALOG CONVERTERS 有权
标题翻译：数字三角形数字转换器非线性误差数字校正
公开(公告)号：US20080150773A1
公开(公告)日：2008-06-26
申请号：US12041204
申请日：2008-03-03
申请人： Jesus ARAIS , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Jesus ARAIS , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H03M1/10
CPC分类号： H03M3/388 , H03M1/0665 , H03M3/424 , H03M3/464
摘要： Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
摘要翻译：提供了用于误差反馈DAC的多位ADAC非线性的数字校正。通过低分辨率校准ADC（CADC）估计多位ADAC的积分非线性（INL）误差（在线或离线）并存储在随机存取存储器（RAM）表中。然后，INL值用于补偿ADAC在数字域中的失真。当这种补偿与DWA等不匹配成形技术相结合时，可以显着放宽CADC的分辨率要求。所提出的用于误差反馈调制器的修正电路的实现本质上是简单的，因为校正仅需要数字求和而不需要任何额外的数字滤波。

9. 发明授权

US06552838B2 LiNbO3 Mach-Zehnder modulator with low drive voltage requirement and adjustable chirp 失效
公开(公告)号：US06552838B2
公开(公告)日：2003-04-22
申请号：US09907420
申请日：2001-07-18
申请人： Johannes G. Ransijn , James D. Yoder
发明人： Johannes G. Ransijn , James D. Yoder
IPC分类号： G02F103
CPC分类号： H04B10/505 , G02F1/0121 , G02F1/2255
摘要： An electro-optic modulator and associated method are provided. The electro-optic modulator includes an optical waveguide comprised of two pairs of coplanar modulation strips, the strips being driven by a controller circuit which applies voltages of equal amplitude and opposite polarity to the strips of each pair. The voltage applied to the first pair of strips may differ from the voltage applied to the second pair of strips, so that a chirp factor may be adjusted if desired. The modulator and associated method exhibit reduced drive voltage requirements.

10. 发明授权

US08867182B2 Signal-powered integrated circuit with ESD protection 有权
标题翻译：具有ESD保护功能的信号供电集成电路
公开(公告)号：US08867182B2
公开(公告)日：2014-10-21
申请号：US12794845
申请日：2010-06-07
申请人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
发明人： Boris A. Bark , Brad L. Grande , Peter Kiss , Johannes G. Ransijn , James D. Yoder
IPC分类号： H02H9/00 , H04M19/00
CPC分类号： H04M19/001
摘要： The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.
摘要翻译：本发明提供一种信号供电的集成电路（IC）。 IC包括集成电路管芯，其包括接地节点，供电节点和用于接收具有数据内容和预定能量的数字数据信号的第一端子。形成在集成电路管芯上的接收缓冲器连接到第一终端并且能够接收与数字数据信号相关联的数据内容。整流器也形成在集成电路管芯上。整流器包括连接在第一端子和接地节点之间的第一二极管和连接在第一端子与供电节点之间的第二二极管。整流器被配置为对数字数据信号进行整流，并将数字数据信号的至少一部分预定能量传递给供电节点。第一和第二二极管中的每一个能够承受ESD冲击。

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