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    • 2. 发明授权
    • Volume control device
    • 音量控制装置
    • US5394476A
    • 1995-02-28
    • US992356
    • 1992-12-17
    • Norman T. RollinsKing F. Lee
    • Norman T. RollinsKing F. Lee
    • H03G3/00H03G3/04H04B1/10
    • H03G3/04H03G3/001
    • A volume control circuit comprises a variable gain stage (306), having a variable gain, and an up/down counter (324) for counting. The counter (324) has a counter input (321) and a counter output (333) for providing a first word (333) for controlling the gain of the gain stage. A microprocessor interface (326) includes an interface output (323) for providing a second word. A digital magnitude comparator (333) compares the first (323) and second (333) words. The comparator having a first input (333) connected to the counter output, a second input connected to the interface output (323), and a comparator output connected to the counter input (321), provides a count signal (329) if the words do not match and for providing a non-count signal (329) if the words match. Thus, responsive to the count signal (329), the up/down counter (324), counts from the first word, in a direction approaching the second word by a least significant bit to form a new first word, for controlling the gain of the gain stage.
    • 音量控制电路包括具有可变增益的可变增益级(306)和用于计数的上/下计数器(324)。 计数器(324)具有用于提供用于控制增益级的增益的第一字(333)的计数器输入(321)和计数器输出(333)。 微处理器接口(326)包括用于提供第二字的接口输出(323)。 数字量值比较器(333)比较第一(323)和第二(333)字。 比较器具有连接到计数器输出端的第一输入端(333),连接到接口输出端(323)的第二输入端和连接到计数器输入端(321)的比较器输出端,如果这些字 如果词匹配,则不匹配并提供非计数信号(329)。 因此,响应计数信号(329),上/下计数器(324)从接近第二个字的方向从第一个字计数最小有效位以形成一个新的第一个字,用于控制增益的增益 增益阶段。
    • 3. 发明授权
    • High-speed low-power flip-flop
    • 高速低功率触发器
    • US5036217A
    • 1991-07-30
    • US360819
    • 1989-06-02
    • Norman T. RollinsGianfranco Gerosa
    • Norman T. RollinsGianfranco Gerosa
    • H03K3/3562
    • H03K3/35625
    • A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal. The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption. The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged.
    • 具有第一双稳态单元的主从触发器和耦合到第一单元的控制电路,用于响应于一组补充数据输入和时钟信号来改变单元的二进制状态。 触发器的从部分包括耦合到第一单元的第二双稳态单元和用于响应于第一单元的输出和时钟信号改变第二单元的状态的第二控制电路。 触发器旨在使用CMOS技术实现,并且能够以低功耗的千兆赫的频率执行。 电路配置是高度对称的,从而主和从部分可以互换。