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1. 发明申请

US20100231286A1 Thermal Sensors For Stacked Dies 有权
标题翻译：热敏传感器用于堆叠模具
公开(公告)号：US20100231286A1
公开(公告)日：2010-09-16
申请号：US12306450
申请日：2007-12-24
申请人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
发明人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
IPC分类号： G01K7/00 , H01L25/04
CPC分类号： G01K7/425 , G01K2213/00 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06589 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.
摘要翻译：本发明涉及一种用于从至少两个热传感器获得温度值的方法，所述温度传感器布置在三维模具结构内的资源上，确定所述模具结构的至少部分三维温度分布，并且控制所述模具的所述资源的活动对所述三维温度分布的响应。

2. 发明授权

US07852138B2 Thermal sensors for stacked dies 有权
标题翻译：用于堆叠模具的热传感器
公开(公告)号：US07852138B2
公开(公告)日：2010-12-14
申请号：US12306450
申请日：2007-12-24
申请人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
发明人： Kimmo Kuusilinna , Jani Klint , Tapio Hill
IPC分类号： H01L35/00
CPC分类号： G01K7/425 , G01K2213/00 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06589 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.
摘要翻译：本发明涉及一种用于从至少两个热传感器获得温度值的方法，所述温度传感器布置在三维模具结构内的资源上，确定所述模具结构的至少部分三维温度分布，并且控制所述模具的所述资源的活动对所述三维温度分布的响应。

3. 发明申请

US20060230250A1 Memory interface for volatile and non-volatile memory devices 有权
标题翻译：用于易失性和非易失性存储器件的存储器接口
公开(公告)号：US20060230250A1
公开(公告)日：2006-10-12
申请号：US11105324
申请日：2005-04-12
申请人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
发明人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
IPC分类号： G06F13/00 , G06F9/34
CPC分类号： G06F13/1694
摘要： Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.
摘要翻译：通过接口访问存储在存储器设备中的数据，通过至少一个地址总线在存储器设备上寻址数据，至少通过至少一个命令总线控制来自存储器设备的数据流，以及从或从通过至少一个数据总线的存储器，其中根据连接到接口的存储器的类型来调整命令总线上的命令。

4. 发明授权

US08635394B2 Method, an interface for volatile and non-volatile memory devices as well as a related computer program product, and a device 有权
标题翻译：方法，用于易失性和非易失性存储器设备的接口以及相关的计算机程序产品和设备
公开(公告)号：US08635394B2
公开(公告)日：2014-01-21
申请号：US11998355
申请日：2007-11-28
申请人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
发明人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.
摘要翻译：通过接口访问存储在存储器设备中的数据，通过至少一个地址总线在存储器设备上寻址数据，至少通过至少一个命令总线控制来自存储器设备的数据流，以及从或从通过至少一个数据总线的存储器，其中根据连接到接口的存储器的类型来调整命令总线上的命令。

5. 发明授权

US07562193B2 Memory with single and dual mode access 有权
标题翻译：内存，单模和双模存取
公开(公告)号：US07562193B2
公开(公告)日：2009-07-14
申请号：US10828516
申请日：2004-04-19
申请人： Matti Floman , Jani Klint
发明人： Matti Floman , Jani Klint
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C8/00
CPC分类号： G11C7/1075 , G11C7/1045
摘要： The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.
摘要翻译：本发明涉及具有用于存储数据的至少两个存储区域的存储器单元，用于访问存储器区域内的数据的第一终端和用于访问存储区域内的数据的第二终端。为了提供对存储器的多用途访问，存储器单元提供至少两个访问控制装置，用于分别通过终端之一提供选择性唯一寻址和访问数据，或分别通过每个终端单独寻址和访问数据。

6. 发明申请

US20060187726A1 Memory bus checking procedure 有权
公开(公告)号：US20060187726A1
公开(公告)日：2006-08-24
申请号：US11400327
申请日：2006-04-06
申请人： Matti Floman , Jani Klint
发明人： Matti Floman , Jani Klint
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G06F11/221 , G11C29/025 , G11C2029/4402
摘要： A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

7. 发明申请

US20060132337A1 Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal 有权
标题翻译：集成电路接口，其使用在时钟信号的两个连续边缘变换处采样的至少一个输入信号对信息进行编码
公开(公告)号：US20060132337A1
公开(公告)日：2006-06-22
申请号：US11003585
申请日：2004-12-02
申请人： Matti Floman , Jani Klint
发明人： Matti Floman , Jani Klint
IPC分类号： H03M7/40
CPC分类号： G06F13/4243 , G11C7/1006 , G11C7/1072
摘要： An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n≧2.
摘要翻译：诸如动态RAM的集成电路包括用于耦合到信号线的多个终端。信号线之一是传送时钟信号的输入信号线，并且至少一条其它信号线也是输入由n个连续边缘上的至少一条其它信号线的电平编码的信息的输入信号线时钟信号的转换，其中n> = 2。

8. 发明申请

US20080162768A1 Memory interface for volatile and non-volatile memory devices 有权
标题翻译：用于易失性和非易失性存储器件的存储器接口
公开(公告)号：US20080162768A1
公开(公告)日：2008-07-03
申请号：US11998355
申请日：2007-11-28
申请人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
发明人： Jani Klint , Sakari Sippola , Matti Floman , Jukka-Pekka Vihmalo
IPC分类号： G06F13/14
CPC分类号： G06F13/1694
摘要： Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.
摘要翻译：通过接口访问存储在存储器设备中的数据，通过至少一个地址总线在存储器设备上寻址数据，至少通过至少一个命令总线控制来自存储器设备的数据流，以及从或从通过至少一个数据总线的存储器，其中根据连接到接口的存储器的类型来调整命令总线上的命令。

9. 发明申请

US20060184726A1 Flexible access and control of Dynamic Random Access Memory 审中-公开
标题翻译：灵活的访问和控制动态随机存取存储器
公开(公告)号：US20060184726A1
公开(公告)日：2006-08-17
申请号：US11057063
申请日：2005-02-11
申请人： Jani Klint , Matti Floman , Jukka-Pekka Vihmalo
发明人： Jani Klint , Matti Floman , Jukka-Pekka Vihmalo
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： The invention relates in general to a method for accessing data stored in a dynamic random access memory. To enable flexible use of different types of memory modules, the invention provides addressing data through at least one address bus, controlling at least data flow to and from the dynamic random access memory through at least one control bus, transferring data to and from the dynamic random access memory through at least one data bus, and clocking the dynamic random access memory through at least one clock input, wherein transferring data to and from the dynamic random access memory through the data bus is operated at a variable data flow rate such that the number of data bits transferred on the data bus within one clock cycle is adjustable through at least one command on the control bus.
摘要翻译：本发明一般涉及用于访问存储在动态随机存取存储器中的数据的方法。为了能够灵活地使用不同类型的存储器模块，本发明通过至少一个地址总线提供寻址数据，至少通过至少一个控制总线控制至少与动态随机存取存储器的数据流，从动态通过至少一个数据总线的随机存取存储器，以及通过至少一个时钟输入对动态随机存取存储器进行计时，其中通过数据总线向动态随机存取存储器传送数据和从数据总线传送数据到可变数据流速，在一个时钟周期内在数据总线上传输的数据位数可通过控制总线上的至少一个命令进行调节。

10. 发明授权

US07057911B2 Memory structure, a system, and an electronic device, as well as a method in connection with a memory circuit 失效
标题翻译：存储器结构，系统和电子设备，以及与存储器电路相关的方法
公开(公告)号：US07057911B2
公开(公告)日：2006-06-06
申请号：US10659067
申请日：2003-09-10
申请人： Jani Klint
发明人： Jani Klint
IPC分类号： G11C15/00
CPC分类号： G06F13/1684 , G06F13/1694
摘要： A memory circuit (1) comprises at least a non-volatile random access memory (3) and a random access memory (4). The memory circuit (1) also comprises a memory controller (5) connected by a first bus (6) to the non-volatile random access memory (3) and by a second bus (10) to the random access memory (4). Thus, data can be transmitted between non-volatile random access memory (3) and random access memory (4) via the memory controller (5). The memory circuit comprises a control bus (12) connected to the memory controller (5) to control operation of the memory circuit (1). The invention also relates to a corresponding system and corresponding electronic device (2) in which the memory circuit (1) is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory (3) and a random access memory (4) are used.
摘要翻译：存储器电路（1）至少包括非易失性随机存取存储器（3）和随机存取存储器（4）。存储器电路（1）还包括通过第一总线（6）连接到非易失性随机存取存储器（3）和通过第二总线（10）连接到随机存取存储器（4）的存储器控制器（5）。因此，可以经由存储器控制器（5）在非易失性随机存取存储器（3）和随机存取存储器（4）之间传输数据。存储器电路包括连接到存储器控制器（5）以控制存储器电路（1）的操作的控制总线（12）。本发明还涉及使用存储电路（1）的相应系统和相应的电子设备（2）。本发明还涉及一种与使用至少一个非易失性随机存取存储器（3）和随机存取存储器（4）的存储器电路相关的方法。

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