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1. 发明授权

US6084255A Gate array semiconductor device 失效
标题翻译：门阵列半导体器件
公开(公告)号：US6084255A
公开(公告)日：2000-07-04
申请号：US126092
申请日：1998-07-30
申请人： Kimio Ueda , Takanori Hirota , Yoshiki Wada , Koichiro Mashiko
发明人： Kimio Ueda , Takanori Hirota , Yoshiki Wada , Koichiro Mashiko
IPC分类号： H01L21/82 , H01L27/02 , H01L27/118 , H01L27/12 , H01L27/10
CPC分类号： H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.
摘要翻译：在以SOI阵列排列的每个基本单元（BC）中，对称地形成PMOS和NMOS晶体管。主体区域（11）和（12）分别形成为分隔源极/漏极层（1）和（2），并且在主体区域（11）和（12）上形成栅电极（3）和（4）分别在其间夹着栅极绝缘膜。栅电极（3）和（4）的两端分别连接到栅极接触区域（5）至（8），并且主体区域（11）和（12）在其一端连接到主体接触区域（9）和（10）。主体接触区域（9）和（10）被布置成分别将栅极接触区域（5）和（7）与栅极电极（3）和（4）夹在一起。作为SOI型，该器件实现了高速操作和低功耗。此外，通过体接触区域（9），（10）和栅极接触区域（5），（7）之间的位置关系，该器件能够自由地将晶体管设置为栅极控制型或栅极固定式。结果，门阵列型半导体器件实现了高速操作和低功耗。

2. 发明授权

US08624683B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08624683B2
公开(公告)日：2014-01-07
申请号：US13105369
申请日：2011-05-11
申请人： Takanori Hirota
发明人： Takanori Hirota
IPC分类号： H03B5/12 , H03B5/18
CPC分类号： H03B5/1215 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03B5/1243
摘要： A semiconductor device is provided which can reduce a parasitic inductor and/or parasitic capacitance added to the wiring that couples spiral inductors and MOS varactors included in a VCO. An LC-tank VCO includes first and second spiral inductors, and first and second MOS varactors. As seen perpendicularly to the semiconductor substrate, the first and second MOS varactors are arranged in a region between the first spiral inductor and the second spiral inductor.
摘要翻译：提供一种半导体器件，其可以减少附加到连接到VCO中的螺旋电感器和MOS可变电抗器的布线的寄生电感器和/或寄生电容。 LC-Tank VCO包括第一和第二螺旋电感器以及第一和第二MOS可变电抗器。如从垂直于半导体衬底看到的那样，第一和第二MOS可变电抗器布置在第一螺旋电感器和第二螺旋电感器之间的区域中。

3. 发明授权

US06861883B2 Semiconductor integrated circuit for phase management of clock domains including PLL circuit 失效
标题翻译：用于时钟域相位管理的半导体集成电路，包括PLL电路
公开(公告)号：US06861883B2
公开(公告)日：2005-03-01
申请号：US10360754
申请日：2003-02-10
申请人： Takanori Hirota , Atsuhiko Ishibashi
发明人： Takanori Hirota , Atsuhiko Ishibashi
IPC分类号： H03K5/00 , H03K5/13 , H03K19/0175 , H03L7/00 , H03L7/06 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/087 , H03L7/099 , H03L7/22
CPC分类号： H03K5/133 , H03K2005/00071 , H03L7/07 , H03L7/0814 , H03L7/0996
摘要： Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta−Td−Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.
摘要翻译：假设A时钟驱动器（102），B时钟驱动器（103）和CMOS缓冲电路（119）中的时钟分别具有延迟值Ta，Tb和Td，延迟值Ta-Td被存储在寄存器电路当选择器电路（114,115,116）的端子“0”被选择时，当端子“0”被切换到“1”时，延迟值Ta-Td-Tb被存储在寄存器电路（118）中， “。因此，确定CMOS缓冲电路（119）的延迟值允许确定A时钟驱动器（102）和B时钟驱动器（103）之间的相位差。

4. 发明授权

US08175205B2 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US08175205B2
公开(公告)日：2012-05-08
申请号：US12883272
申请日：2010-09-16
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

5. 发明申请

US20070018704A1 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US20070018704A1
公开(公告)日：2007-01-25
申请号：US11477597
申请日：2006-06-30
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H03K5/01
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译： PD检测VDL与DATA与VDL输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当根据PD的检测结果改变控制码时，当输出时钟与数据信号同步期间，当VDL的延迟量超过时钟的一个周期时，对应于等于一个周期的延迟的控制码的输出时钟被一次添加到/从控制码中减去。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

6. 发明申请

US20110007855A1 Clock Data Recovery Circuit Capable of Generating Clock Signal Synchronized with Data Signal 失效
标题翻译：能够产生与数据信号同步的时钟信号的时钟数据恢复电路
公开(公告)号：US20110007855A1
公开(公告)日：2011-01-13
申请号：US12883272
申请日：2010-09-16
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

7. 发明授权

US07822158B2 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US07822158B2
公开(公告)日：2010-10-26
申请号：US11477597
申请日：2006-06-30
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

8. 发明授权

US5945843A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5945843A
公开(公告)日：1999-08-31
申请号：US950421
申请日：1997-10-24
申请人： Takanori Hirota , Yasushi Hayakawa
发明人： Takanori Hirota , Yasushi Hayakawa
IPC分类号： H03K19/086 , H03K19/0175
CPC分类号： H03K19/017527
摘要： A level conversion circuit as a semiconductor integrated circuit has a first load resistance (R1), a second load resistance (R2), a first NMOS transistor (MN3) and a second NMOS transistor (MN4) connected to them (R1 and R2) in parallel, respectively, that are driven directly by positive CMOS level signals, a first bipolar transistor (Q1), and a second bipolar transistor (Q2). Both emitters of the first and second bipolar transistors (Q1 and Q2) are connected commonly, and a voltage potential that is lower than a voltage potential of a collector of the first bipolar transistor (Q1) by a predetermined voltage potential is supplied into a base of the second bipolar transistor (Q2).
摘要翻译：作为半导体集成电路的电平转换电路具有与其连接的第一负载电阻（R1），第二负载电阻（R2），第一NMOS晶体管（MN3）和第二NMOS晶体管（MN4）（R1和R2）分别由正CMOS电平信号直接驱动，第一双极晶体管（Q1）和第二双极晶体管（Q2）并联。第一和第二双极晶体管（Q1和Q2）的两个发射极共同连接，并且将低于预定电压电位的第一双极晶体管（Q1）的集电极的电压电位的电压电位供给到基极的第二双极晶体管（Q2）。

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