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1. 发明授权

US5350939A Semiconductor device and method of manufacturing thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5350939A
公开(公告)日：1994-09-27
申请号：US37141
申请日：1993-03-25
申请人： Hiroki Honda , Kimiharu Uga , Masahiro Ishida , Yoshiyuki Ishigaki
发明人： Hiroki Honda , Kimiharu Uga , Masahiro Ishida , Yoshiyuki Ishigaki
IPC分类号： H01L21/74 , H01L21/76 , H01L27/06 , H01L27/08 , H01L27/02
CPC分类号： H01L27/0623
摘要： An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.
摘要翻译： n型外延层4形成在p型半导体衬底1的顶面上。通过在p型半导体衬底1和n外延层4上延伸的区域中注入离子形成p +埋层20。通过离子注入在p +掩埋层20的上层形成沟道阻挡层。形成从p +沟道阻挡层的上层延伸到n外延层的顶面的p阱。在p阱22中形成n沟道MOS型场效应晶体管200.由于结构，可以将元件与相邻元件可靠地隔离。

2. 发明授权

US5355009A Semiconductor device and method of fabricating same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5355009A
公开(公告)日：1994-10-11
申请号：US875019
申请日：1992-04-28
申请人： Hiroki Honda , Kimiharu Uga , Masahiro Ishida , Yoshiyuki Ishigaki
发明人： Hiroki Honda , Kimiharu Uga , Masahiro Ishida , Yoshiyuki Ishigaki
IPC分类号： H01L21/8249 , H01L29/732 , H01L27/02
CPC分类号： H01L29/7322 , H01L21/8249
摘要： Insulator films (5) formed on an epitaxial layer (3) are opened such that external base regions (17) are not covered with the insulator films (5). Cross sections (14a) of the insulator films (5) are concavely sloped downward from the insulator films (5) toward an intrinsic base region (18) in the vicinity of the epitaxial layer (3). Base electrodes (15) which are in contact with the insulator films (5) along the cross sections (14a) are connected to the external base regions (17), so that coverage of the base electrodes (15) over the external base regions (17) is improved. The base resistance of a bipolar transistor (101) is reduced.
摘要翻译：形成在外延层（3）上的绝缘体膜（5）被打开，使得外部基极区域（17）未被绝缘膜（5）覆盖。绝缘体膜（5）的横截面（14a）从绝缘体膜（5）朝向外延层（3）附近的本征基极区域（18）向下凹下倾斜。与绝缘膜（5）沿着横截面（14a）接触的基极（15）连接到外部基极区域（17），使得基极（15）在外部基极区域 17）得到改善。双极晶体管（101）的基极电阻减小。

3. 发明授权

US5480816A Method of fabricating a bipolar transistor having a link base 失效
标题翻译：制造具有连接座的双极晶体管的方法
公开(公告)号：US5480816A
公开(公告)日：1996-01-02
申请号：US273915
申请日：1994-07-12
申请人： Kimiharu Uga , Hiroki Honda , Masahiro Ishida , Yoshiyuki Ishigaki
发明人： Kimiharu Uga , Hiroki Honda , Masahiro Ishida , Yoshiyuki Ishigaki
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732 , H01L21/265 , H01L21/225 , H01L21/385
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/7322
摘要： On an epitaxial layer (4) serving as a collector layer are formed an emitter layer (10), an intrinsic base layer (9) surrounding the emitter layer (10) while permitting the surface of the emitter layer (10) to be exposed, external base layers (8) and link base layers (7) lying between the intrinsic base layer (9) and external base layers (8). The intrinsic base layer between the emitter layer and the epitaxial layer serving as the collector layer has a relatively high impurity concentration, so that a collector-emitter breakdown voltage is not decreased. The link base layers between the intrinsic base layer and external base layers has a relatively low impurity concentration to suppress decrease in emitter-base junction breakdown voltage.
摘要翻译：在用作集电极层的外延层（4）上形成发射极层（10），包围发射极层（10）的本征基极层（9），同时允许发射极层（10）的表面露出，位于本征基底层（9）和外部基底层（8）之间的外部基底层（8）和连接基底层（7）。用作集电极层的发射极层和外延层之间的本征基极层具有较高的杂质浓度，使得集电极 - 发射极击穿电压不降低。本征基极层和外部基极层之间的基极层具有相对低的杂质浓度，以抑制发射极 - 基极结击穿电压的降低。

4. 发明授权

US5471085A Semiconductor device with polycrystalline silicon emitter conductive layer 失效
标题翻译：具有多晶硅发射极导电层的半导体器件
公开(公告)号：US5471085A
公开(公告)日：1995-11-28
申请号：US310526
申请日：1994-09-22
申请人： Yoshiyuki Ishigaki , Hiroki Honda , Kimiharu Uga , Masahiro Ishida
发明人： Yoshiyuki Ishigaki , Hiroki Honda , Kimiharu Uga , Masahiro Ishida
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/417 , H01L29/732 , H01L29/72
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/41708
摘要： An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.
摘要翻译：在p-半导体衬底的表面上形成n +掩埋层。在n +掩埋层的表面上形成n外延生长层和n +扩散层。在n-外延生长层的表面上形成彼此相邻的p-基区和p +外基区。在p基极区的表面形成n +射极区。发射极电极与n +发射极区域相邻形成。发射电极由掺杂浓度为1×10 20 cm -3至6×10 20 cm -3的磷的多晶硅制成。

5. 发明授权

US5319234A C-BiCMOS semiconductor device 失效
标题翻译： C-BiCMOS半导体器件
公开(公告)号：US5319234A
公开(公告)日：1994-06-07
申请号：US916666
申请日：1992-07-22
申请人： Kimiharu Uga , Hiroki Honda , Masahiro Ishida , Yoshiyuki Ishigaki
发明人： Kimiharu Uga , Hiroki Honda , Masahiro Ishida , Yoshiyuki Ishigaki
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/02
CPC分类号： H01L27/0623
摘要： There is disclosed a C-BiCMOS semiconductor device in which a base electrode (300) of an NPN bipolar transistor and a drain electrode (360) of a PMOS transistor are formed of the same polycrystalline semiconductor, in which a base electrode (310) of a PNP bipolar transistor and a drain electrode (350) of an NMOS transistor are formed of the same polycrystalline semiconductor, and in which a source electrode (530) of the PMOS transistor and a source electrode (520) of the NMOS transistor are formed of aluminium wiring. The C-BiCMOS semiconductor device achieves preferable electric conductivity in the source electrodes, size reduction in the drain electrodes, and simplified process steps in the formation of the base electrodes of the bipolar transistors, so that the size of the devices is reduced in simple process steps without deterioration of the electric conductivity.
摘要翻译：公开了一种C-BiCMOS半导体器件，其中NPN双极晶体管的基极（300）和PMOS晶体管的漏电极（360）由相同的多晶半导体形成，其中基极（310）为 NMOS晶体管的PNP双极晶体管和漏电极（350）由相同的多晶半导体形成，其中PMOS晶体管的源电极（530）和NMOS晶体管的源电极（520）由铝接线。 C-BiCMOS半导体器件在源电极中实现优选的导电性，漏电极的尺寸减小，以及双极晶体管的基极形成中的简化工艺步骤，从而在简单的工艺中减小器件的尺寸步骤不劣化导电性。

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