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1. 发明授权

US09180608B2 Stamp, method of manufacturing the same, and imprinting method using the stamp 有权
标题翻译：印章，制造方法和使用印章的印记方法
公开(公告)号：US09180608B2
公开(公告)日：2015-11-10
申请号：US13489968
申请日：2012-06-06
申请人： Woong Ko , Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Jae-kwan Kim
发明人： Woong Ko , Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Jae-kwan Kim
IPC分类号： B29C33/38 , B29C33/42 , B29C43/02
CPC分类号： B29C33/424 , B29C43/021 , B29C2043/025
摘要： A stamp includes at least one protrusion on a protrusion pattern, and an end portion of the at least one protrusion may have a non-planarized surface. The end portion of the protrusion may have a concave structure, that is, the end portion includes a center region and an edge region, and the edge region is higher than the center region.
摘要翻译：印模包括在突起图案上的至少一个突起，并且所述至少一个突起的端部可以具有非平坦化表面。突起的端部可以具有凹形结构，即，端部包括中心区域和边缘区域，并且边缘区域高于中心区域。

2. 发明授权

US09333682B2 Stamp, method of fabricating the stamp, and imprint method using the same 有权
标题翻译：印章，制作印章的方法，以及使用印章的印记法
公开(公告)号：US09333682B2
公开(公告)日：2016-05-10
申请号：US13620219
申请日：2012-09-14
申请人： Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Woong Ko , Jae-kwan Kim
发明人： Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Woong Ko , Jae-kwan Kim
IPC分类号： B29C43/02 , G03F7/00 , B29C43/10 , B82Y10/00 , B82Y40/00 , B29C43/32 , B29C43/36
CPC分类号： B29C43/021 , B29C43/10 , B29C2043/025 , B29C2043/3233 , B29C2043/3238 , B29C2043/3615 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： A stamp includes a transparent body having an inner chamber containing an inlet/outlet tube configured to have a fluid injected and removed therefrom.
摘要翻译：邮票包括具有内部腔室的透明主体，该内部腔室包括被配置为具有从其喷射和移除的流体的入口/出口管。

3. 发明授权

US09360751B2 Imprinting stamp and nano-imprinting method using the same 有权
标题翻译：印记邮票和使用相同的纳米印记法
公开(公告)号：US09360751B2
公开(公告)日：2016-06-07
申请号：US13617874
申请日：2012-09-14
申请人： Ki-yeon Yang , Woong Ko , Jae-kwan Kim , Du-hyun Lee , Byung-kyu Lee
发明人： Ki-yeon Yang , Woong Ko , Jae-kwan Kim , Du-hyun Lee , Byung-kyu Lee
IPC分类号： G03F7/00 , B29C59/02 , B82Y10/00 , B82Y40/00
CPC分类号： G03F7/0002 , B29C59/022 , B82Y10/00 , B82Y40/00 , Y10S977/887
摘要： An imprinting stamp and a nano-imprinting method using the imprinting stamp are provided. The imprinting stamp includes a first substrate; one or more field regions on the first substrate, the first substrate including nano-patterns; and a first dummy pattern region on the first substrate and adjacent to the field region, the dummy pattern region including first dummy patterns having greater dimensions than that of the nano-patterns, the first dummy patterns being a plurality of polygons, each of the polygons having a vertex pointing in a first direction proceeding from the field region toward the first dummy pattern region.
摘要翻译：提供使用印记印记的印记印记和纳米印记法。印记印模包括第一基板; 所述第一基板上的一个或多个场区域，所述第一基板包括纳米图案; 以及在所述第一基板上并且与所述场区域相邻的第一虚设图案区域，所述虚设图案区域包括具有比所述纳米图案的尺寸更大的尺寸的第一虚设图案，所述第一虚设图案是多个多边形，每个所述多边形具有指向从场区域朝向第一虚拟图案区域的第一方向的顶点。

4. 发明申请

US20130042779A1 STAMP, METHOD OF MANUFACTURING THE SAME, AND IMPRINTING METHOD USING THE STAMP 有权
标题翻译：印章，其制造方法和使用印章的印刷方法
公开(公告)号：US20130042779A1
公开(公告)日：2013-02-21
申请号：US13489968
申请日：2012-06-06
申请人： Woong Ko , Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Jae-kwan Kim
发明人： Woong Ko , Ki-yeon Yang , Byung-kyu Lee , Du-hyun Lee , Jae-kwan Kim
IPC分类号： B41F19/00 , B29C33/38 , B41N1/00
CPC分类号： B29C33/424 , B29C43/021 , B29C2043/025
摘要： A stamp includes at least one protrusion on a protrusion pattern, and an end portion of the at least one protrusion may have a non-planarized surface. The end portion of the protrusion may have a concave structure, that is, the end portion includes a center region and an edge region, and the edge region is higher than the center region.
摘要翻译：印模包括在突起图案上的至少一个突起，并且所述至少一个突起的端部可以具有非平坦化表面。突起的端部可以具有凹形结构，即，端部包括中心区域和边缘区域，并且边缘区域高于中心区域。

5. 发明申请

US20080100346A1 Method and apparatus for measuring pulse widths of a side-band signal 失效
标题翻译：用于测量边带信号的脉冲宽度的方法和装置
公开(公告)号：US20080100346A1
公开(公告)日：2008-05-01
申请号：US11976922
申请日：2007-10-30
申请人： Hyung-seuk Kim , Jae-kwan Kim
发明人： Hyung-seuk Kim , Jae-kwan Kim
IPC分类号： G01R29/02
CPC分类号： H03K9/08 , H03K5/1565
摘要： Example embodiments are directed to an apparatus and method for measuring a pulse width. A side-band signal generator may be configured to receive a given data pattern and output a side-band signal by modulating a pulse width of the received data pattern in a test mode. A phase detector may be configured to receive the side-band signal and a reference clock signal, and output a pulse signal corresponding to a phase difference between the received side-band signal and the reference clock signal. A charge pump may be configured to receive the pulse signal and output an output voltage by increasing or decreasing the output voltage based on the pulse signal. A pulse width measurer may be configured to receive the output voltage of the charge pump and determine whether pulses forming the side-band signal have appropriate widths based on whether the output voltage is included in a desired reference voltage range.
摘要翻译：示例性实施例涉及用于测量脉冲宽度的装置和方法。侧带信号发生器可以被配置为通过在测试模式中调制所接收的数据模式的脉冲宽度来接收给定的数据模式并输出边带信号。相位检测器可以被配置为接收边带信号和参考时钟信号，并且输出与接收的边带信号和参考时钟信号之间的相位差对应的脉冲信号。电荷泵可以被配置为通过基于脉冲信号增加或减小输出电压来接收脉冲信号并输出输出电压。脉冲宽度测量器可以被配置为接收电荷泵的输出电压，并且基于输出电压是否包括在期望的参考电压范围来确定形成边带信号的脉冲是否具有适当的宽度。

6. 发明授权

US07538573B2 Dynamic output buffer circuit 有权
标题翻译：动态输出缓冲电路
公开(公告)号：US07538573B2
公开(公告)日：2009-05-26
申请号：US11705251
申请日：2007-02-12
申请人： Jae-kwan Kim , Joo-sun Choi
发明人： Jae-kwan Kim , Joo-sun Choi
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0288
摘要： A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.
摘要翻译：动态输出缓冲电路通过使用输入和输出信号来执行阻抗匹配功能和预加重功能，并且消耗相对较小的功率，占据相对较小的布局面积，并且动态地改变输出阻抗。动态输出缓冲电路将输出阻抗与连接到外部电路的金属线的特性阻抗动态匹配，预先强调至少一个输入信号，并且包括控制电路和输出电路。响应于至少一个输出信号，控制电路将动态输出电路的输出阻抗与金属线的特性阻抗相匹配，并输出多个电阻控制信号，用于预先强调至少一个输入信号响应输入信号。输出电路控制输出阻抗，并响应于电阻控制信号预加强输入信号，并输出输出信号。

7. 发明授权

US07117381B2 Control signal generation circuit and data transmission circuit having the same 失效
标题翻译：控制信号发生电路和数据传输电路具有相同的功能
公开(公告)号：US07117381B2
公开(公告)日：2006-10-03
申请号：US10750896
申请日：2004-01-05
申请人： Jae-kwan Kim , Jung-hwan Choi
发明人： Jae-kwan Kim , Jung-hwan Choi
IPC分类号： G06F1/04
CPC分类号： G06F5/06
摘要： A data transmission circuit includes a control signal generation circuit, a write state machine, a conversion circuit, a read state machine, and a selection circuit. The control signal generation circuit receives a strobe signal and a clock signal in response to an enable signal, generates a write control signal that is activated in response to a rising edge of the strobe signal, and generates a read control signal that is activated in response to a first rising or falling edge of the clock signal after the write control signal is activated. The write state machine is activated in response to the write control signal, changes its internal state in synchronization with the strobe signal, and sequentially outputs input control signals in response to the changed internal state. The conversion circuit converts serial data to parallel data in response to the input control signal sequentially output from the write state machine and latches the parallel data. The read state machine is activated in response to the read control signal, changes its internal state in synchronization with the clock signal, and sequentially outputs output control signals in response to the changed internal state. The selection circuit outputs the parallel data latched in the conversion circuit in the same order that the serial data is sequentially input to the conversion circuit in response to the output control signals sequentially output from the read state machine.
摘要翻译：数据传输电路包括控制信号产生电路，写状态机，转换电路，读状态机和选择电路。控制信号发生电路响应于使能信号接收选通信号和时钟信号，产生响应于选通信号的上升沿被激活的写入控制信号，并产生响应中被激活的读取控制信号在写入控制信号被激活之后到时钟信号的第一个上升沿或下降沿。写状态机响应于写入控制信号被激活，与选通信号同步地改变其内部状态，并响应于改变的内部状态顺序地输出输入控制信号。转换电路响应于从写入状态机顺序地输出的输入控制信号将串行数据转换为并行数据并锁存并行数据。读取状态机响应于读取控制信号被激活，与时钟信号同步地改变其内部状态，并且响应于改变的内部状态顺序地输出输出控制信号。选择电路响应于从读取状态机顺序地输出的输出控制信号，以与顺序地将串行数据顺序地输入到转换电路的顺序相同的顺序输出锁存在转换电路中的并行数据。

8. 发明授权

US08015336B2 Method of compensating for propagation delay of tri-state bidirectional bus in a semiconductor device 有权
标题翻译：补偿半导体器件中三态双向总线传播延迟的方法
公开(公告)号：US08015336B2
公开(公告)日：2011-09-06
申请号：US11949176
申请日：2007-12-03
申请人： Jae-kwan Kim
发明人： Jae-kwan Kim
IPC分类号： G06F13/00
CPC分类号： H04L7/0008 , H04L7/04
摘要： A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block and each of the slave blocks and accommodates transmission of data therebetween. A unidirectional bus is connected between the master block and each of the slave blocks. The unidirectional bus accommodates the transmission of control signals generated in the master block to the slave blocks wherein the master block detects a propagation delay time between the master block and the slave blocks. The master block counts the number of clocks from a time when a selected slave block transmits an allocated symbol to a time when the allocated symbol reaches the master block such that a propagation delay time between the master block and the selected slave block is detected and stored.
摘要翻译：一种用于检测和补偿连接在主块和多个从块之间的三态双向总线的传播延迟的半导体器件。主站控制从站。双向总线连接主块和每个从块，并适应其间的数据传输。主模块和每个从模块之间连接有单向总线。单向总线适应在主块中产生的控制信号到从属块的传输，其中主块检测主块和从属块之间的传播延迟时间。主块对所选择的从块发送分配符号的时间计数到分配的符号到达主块的时间，从而检测并存储主块与所选择的从块之间的传播延迟时间。

9. 发明授权

US07656147B2 Method and apparatus for measuring pulse widths of a side-band signal 失效
标题翻译：用于测量边带信号的脉冲宽度的方法和装置
公开(公告)号：US07656147B2
公开(公告)日：2010-02-02
申请号：US11976922
申请日：2007-10-30
申请人： Hyung-seuk Kim , Jae-kwan Kim
发明人： Hyung-seuk Kim , Jae-kwan Kim
IPC分类号： G01R25/00 , H01D13/00 , H03K7/08 , H03L7/06
CPC分类号： H03K9/08 , H03K5/1565
摘要： Example embodiments are directed to an apparatus and method for measuring a pulse width. A side-band signal generator may be configured to receive a given data pattern and output a side-band signal by modulating a pulse width of the received data pattern in a test mode. A phase detector may be configured to receive the side-band signal and a reference clock signal, and output a pulse signal corresponding to a phase difference between the received side-band signal and the reference clock signal. A charge pump may be configured to receive the pulse signal and output an output voltage by increasing or decreasing the output voltage based on the pulse signal. A pulse width measurer may be configured to receive the output voltage of the charge pump and determine whether pulses forming the side-band signal have appropriate widths based on whether the output voltage is included in a desired reference voltage range.
摘要翻译：示例性实施例涉及用于测量脉冲宽度的装置和方法。侧带信号发生器可以被配置为通过在测试模式中调制所接收的数据模式的脉冲宽度来接收给定的数据模式并输出边带信号。相位检测器可以被配置为接收边带信号和参考时钟信号，并且输出与接收的边带信号和参考时钟信号之间的相位差对应的脉冲信号。电荷泵可以被配置为通过基于脉冲信号增加或减小输出电压来接收脉冲信号并输出输出电压。脉冲宽度测量器可以被配置为接收电荷泵的输出电压，并且基于输出电压是否包括在期望的参考电压范围来确定形成边带信号的脉冲是否具有适当的宽度。

10. 发明授权

US07512845B2 Semiconductor memory device and method for stacking reference data 失效
标题翻译：用于堆叠参考数据的半导体存储器件和方法
公开(公告)号：US07512845B2
公开(公告)日：2009-03-31
申请号：US10863518
申请日：2004-06-09
申请人： Jae-kwan Kim
发明人： Jae-kwan Kim
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/38
摘要： A semiconductor memory device for compensating latency by stacking reference data. The semiconductor memory device compensates the latency and test errors between two signals by detecting the latency of the two signals and stacking the reference data without using an extra signal. Accordingly, a system can be simplified and power consumption can be reduced when testing the semiconductor memory device, since the extra circuit is unnecessary to synchronize a data sync signal with output data.
摘要翻译：一种用于通过堆叠参考数据来补偿等待时间的半导体存储器件。半导体存储器件通过检测两个信号的等待时间并叠加参考数据而不使用额外的信号来补偿两个信号之间的等待时间和测试误差。因此，由于额外的电路不需要使数据同步信号与输出数据同步，所以可以简化系统并测试半导体存储器件的功耗。

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