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    • 2. 发明申请
    • APPARATUS AND METHOD FOR GENERATING POLITE EXPRESSIONS FOR AUTOMATIC TRANSLATION
    • 用于生成用于自动翻译的波纹表达的装置和方法
    • US20130297284A1
    • 2013-11-07
    • US13566486
    • 2012-08-03
    • Sung-Kwon ChoiOh-Woog KwonKi-Young LeeYoon-Hyung RohYoung-Kil KimSang-Kyu Park
    • Sung-Kwon ChoiOh-Woog KwonKi-Young LeeYoon-Hyung RohYoung-Kil KimSang-Kyu Park
    • G06F17/28
    • G06F17/28
    • Disclosed herein are an apparatus and method for generating polite expressions for automatic translation. The apparatus includes a relationship recognition unit, a polite level selection unit, and a translation unit. The relationship recognition unit extracts relationship information from a conversation between first and second language users and personal information of the first and second language users and then recognizes the social relationship between the language users. The polite level selection unit selects a polite level for the conversation between the first and second language users based on the extracted relationship information. The translation unit generates polite expressions corresponding to the selected polite level, and translates the conversation between the first and second language users into a target language based on the generated polite expressions.
    • 这里公开了一种用于产生用于自动翻译的礼貌表达的装置和方法。 该装置包括关系识别单元,礼貌级别选择单元和翻译单元。 关系识别单元从第一语言用户和第二语言用户之间的对话提取关系信息以及第一和第二语言用户的个人信息,然后识别语言用户之间的社会关系。 礼貌级别选择单元基于所提取的关系信息为第一语言用户和第二语言用户之间的会话选择礼貌级别。 翻译单元生成对应于所选礼貌级别的礼貌表达,并且基于所生成的礼貌表达,将第一语言用户和第二语言用户之间的对话转换为目标语言。
    • 8. 发明授权
    • Method for fabricating an integrated circuit capacitor
    • 集成电路电容器的制造方法
    • US06479850B2
    • 2002-11-12
    • US09968884
    • 2001-10-03
    • Ki-Young Lee
    • Ki-Young Lee
    • H01L27108
    • H01L28/40H01L28/60H01L28/75Y10S438/978
    • A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a “conductivity layer/capping metal layer” deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole. A dielectric layer, devoid of step coverage defects and concentrated electric fields, is inserted in the via hole between the lower and upper electrodes thereby preventing current leakage and short circuits at portions of the dielectric layer. This has the beneficial effect of substantially improving product yield and reliability.
    • 一种用于制造半导体器件的MDL逻辑或模拟电路的MIM电容器的方法。 在具有第一层间绝缘层的半导体衬底上形成导电层。 在导电层上形成具有高于氧化物层的蚀刻速率的覆盖金属层。 通过选择性地蚀刻封盖金属层和导电层来形成包括“导电层/覆盖金属层”沉积的下电极,以暴露第一层间绝缘层的表面的预定部分。 在覆盖下电极的第一层间绝缘层上形成第二层间绝缘层。 通过选择性地蚀刻第二层间绝缘层和下电极来形成通孔,从而露出下电极的一部分,使得锥形封盖金属层沿着通孔的下边缘保留。 在上下电极之间的通孔中插入没有台阶覆盖缺陷和集中电场的电介质层,从而防止电介质层部分的电流泄漏和短路。 这具有显着提高产品产量和可靠性的有益效果。