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1. 发明授权

US07103493B2 Memory testing apparatus and method 有权
标题翻译：记忆体检测装置及方法
公开(公告)号：US07103493B2
公开(公告)日：2006-09-05
申请号：US10851151
申请日：2004-05-24
申请人： Ki-Sang Kang , Tsutomu Akiyama , Je-Young Park
发明人： Ki-Sang Kang , Tsutomu Akiyama , Je-Young Park
IPC分类号： G01R31/00
CPC分类号： G11C29/56004 , G11C29/56 , G11C2029/1208
摘要： Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
摘要翻译：提供了一种操作这样的装置的存储器件测试装置和方法，其可以减少测试诸如DRAM的存储器件所需的时间。存储器测试装置包括模式发生器，测试头，地址指针，选择器，故障存储器，故障位计数器和用于协调各种元件的操作的控制器。根据从控制器接收到的信号，模式发生器将产生背景模式或测试模式和地址信息，这些模式和地址信息又被输出到被测存储器件和选择器。在存储器件的功能测试期间，故障数据被累积在故障存储器中，随后当将背景或测试模式写入存储器件时，使用来自地址指针的地址信息将其输出到故障位计数器。

2. 发明申请

US20050043912A1 Memory testing apparatus and method 有权
标题翻译：记忆体检测装置及方法
公开(公告)号：US20050043912A1
公开(公告)日：2005-02-24
申请号：US10851151
申请日：2004-05-24
申请人： Ki-Sang Kang , Tsutomu Akiyama , Je-Young Park
发明人： Ki-Sang Kang , Tsutomu Akiyama , Je-Young Park
IPC分类号： G01R31/3183 , G01R31/28 , G11C29/00 , G11C29/56 , H01L21/66 , G06F19/00
CPC分类号： G11C29/56004 , G11C29/56 , G11C2029/1208
摘要： Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
摘要翻译：提供了一种操作这样的装置的存储器件测试装置和方法，其可以减少测试诸如DRAM的存储器件所需的时间。存储器测试装置包括模式发生器，测试头，地址指针，选择器，故障存储器，故障位计数器和用于协调各种元件的操作的控制器。根据从控制器接收到的信号，模式发生器将产生背景模式或测试模式和地址信息，这些模式和地址信息又被输出到被测存储器件和选择器。在对存储器件进行功能测试期间，故障数据被累积在故障存储器中，并且随后当将背景或测试模式写入存储器件时，使用来自地址指针的地址信息将其输出到故障位计数器。

3. 发明申请

US20070162794A1 Semiconductor memory test device and method thereof 有权
标题翻译：半导体存储器测试装置及其方法
公开(公告)号：US20070162794A1
公开(公告)日：2007-07-12
申请号：US11640893
申请日：2006-12-19
申请人： Je-Young Park , Ki-Sang Kang
发明人： Je-Young Park , Ki-Sang Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/1806 , G11C2029/5606
摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
摘要翻译：提供半导体存储器测试装置及其方法。示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号，多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

4. 发明申请

US20090199059A1 Semiconductor memory test device and method thereof 有权
公开(公告)号：US20090199059A1
公开(公告)日：2009-08-06
申请号：US12385116
申请日：2009-03-31
申请人： Je-Young Park , Ki-Sang Kang
发明人： Je-Young Park , Ki-Sang Kang
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/1806 , G11C2029/5606
摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

5. 发明授权

US07886206B2 Semiconductor memory test device and method thereof 有权
标题翻译：半导体存储器测试装置及其方法
公开(公告)号：US07886206B2
公开(公告)日：2011-02-08
申请号：US12385116
申请日：2009-03-31
申请人： Je-Young Park , Ki-Sang Kang
发明人： Je-Young Park , Ki-Sang Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/1806 , G11C2029/5606
摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
摘要翻译：提供半导体存储器测试装置及其方法。示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号，多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

6. 发明授权

US07533310B2 Semiconductor memory test device and method thereof 有权
标题翻译：半导体存储器测试装置及其方法
公开(公告)号：US07533310B2
公开(公告)日：2009-05-12
申请号：US11640893
申请日：2006-12-19
申请人： Je-Young Park , Ki-Sang Kang
发明人： Je-Young Park , Ki-Sang Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/1806 , G11C2029/5606
摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
摘要翻译：提供半导体存储器测试装置及其方法。示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号，多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

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