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1. 发明授权

US07494845B2 Method of forming a thin wafer stack for a wafer level package 有权
标题翻译：形成用于晶片级封装的薄晶片叠层的方法
公开(公告)号：US07494845B2
公开(公告)日：2009-02-24
申请号：US11144213
申请日：2005-06-02
申请人： Hyeon Hwang , Ki-Kwon Jeong
发明人： Hyeon Hwang , Ki-Kwon Jeong
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L23/481 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2224/02372 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05548 , H01L2224/16 , H01L2224/2919 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.
摘要翻译：形成薄晶片堆叠的方法提供了晶片级堆叠，以便在晶片被锯切之后分开分离的芯片的方法中大大减少处理时间。刚性平面晶片支撑构件在其薄或其厚度减小和在随后的晶片处理期间稳定和平坦化每个晶片。将薄的晶片堆叠并且通过向支撑构件和薄晶片之间的可扩张的粘合剂层施加热或紫外线（UV）光来去除外部支撑构件。然后可以进一步处理和封装堆叠的晶片，而不会出现薄片翘曲，开裂或断裂。还公开了根据本发明方法制造的晶片级封装。

2. 发明授权

US07262114B2 Die attaching method of semiconductor chip using warpage prevention material 有权
标题翻译：使用防翘曲材料制造半导体芯片的贴片方法
公开(公告)号：US07262114B2
公开(公告)日：2007-08-28
申请号：US11045078
申请日：2005-01-31
申请人： Ki-kwon Jeong , Hyeon Hwang
发明人： Ki-kwon Jeong , Hyeon Hwang
IPC分类号： H01L21/46
CPC分类号： H01L21/78 , H01L21/6835 , H01L2221/68318 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368 , H01L2221/6839
摘要： A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.
摘要翻译：半导体芯片的管芯附接方法简化了从芯片制造封装的过程，同时防止芯片形式受损，即使芯片非常薄。防翘曲材料附着在其上形成有多个芯片的晶片的顶表面上，然后切割晶片以将芯片彼此分离。然后将每个半导体芯片放置并附接到基架的芯片焊盘，同时防止翘曲材料与半导体芯片分离。因此，除去防翘曲材料，而不需要与模具附接工艺无关的工艺。

3. 发明申请

US20050282374A1 Method of forming a thin wafer stack for a wafer level package 有权
标题翻译：形成用于晶片级封装的薄晶片叠层的方法
公开(公告)号：US20050282374A1
公开(公告)日：2005-12-22
申请号：US11144213
申请日：2005-06-02
申请人： Hyeon Hwang , Ki-Kwon Jeong
发明人： Hyeon Hwang , Ki-Kwon Jeong
IPC分类号： H01L23/12 , H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L21/60 , H01L21/68 , H01L21/98 , H01L23/48 , H01L25/065
CPC分类号： H01L21/6835 , H01L23/481 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/6834 , H01L2224/02372 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05548 , H01L2224/16 , H01L2224/2919 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.
摘要翻译：形成薄晶片堆叠的方法提供了晶片级堆叠，以便在晶片被锯切之后分开分离的芯片的方法中大大减少处理时间。刚性平面晶片支撑构件在其薄或其厚度减小和在随后的晶片处理期间稳定和平坦化每个晶片。将薄的晶片堆叠并且通过向支撑构件和薄晶片之间的可扩张的粘合剂层施加热或紫外线（UV）光来去除外部支撑构件。然后可以进一步处理和封装堆叠的晶片，而不会出现薄片翘曲，开裂或断裂。还公开了根据本发明方法制造的晶片级封装。

4. 发明授权

US07294531B2 Wafer level chip stack method 失效
标题翻译：晶圆级芯片堆叠方式
公开(公告)号：US07294531B2
公开(公告)日：2007-11-13
申请号：US10944002
申请日：2004-09-20
申请人： Hyeon Hwang , Dong-Kuk Kim , Ki-Kwon Jeong
发明人： Hyeon Hwang , Dong-Kuk Kim , Ki-Kwon Jeong
IPC分类号： H01L21/00 , H01L21/301
CPC分类号： H01L24/27 , H01L21/67132 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L24/29 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2221/68354 , H01L2221/68368 , H01L2224/274 , H01L2224/32145 , H01L2224/83001 , H01L2224/83191 , H01L2224/8385 , H01L2224/97 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/07802 , H01L2924/12042 , H01L2224/83 , H01L2924/00
摘要： Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.
摘要翻译：提供了可以在晶片级堆叠不同大小的芯片的方法。晶片级芯片堆叠方法利用在胶带上支撑第一和第二晶片的第一和第二晶片组件。支撑的晶片中的一个或两个可以锯切或以其他方式分割，以获得保持固定到相应的第一环形框架的分离的第一和第二芯片。然后可以将第一和第二晶片组件定位和对准，使得第二晶片的后表面面向第一晶片的有效表面。然后可以将每个第二芯片结合到相应的第一芯片以使用粘合剂层形成芯片堆叠。然后可以将芯片堆叠从晶片组件分离并附接到衬底。

5. 发明授权

US07479455B2 Method for manufacturing semiconductor wafer 有权
标题翻译：制造半导体晶片的方法
公开(公告)号：US07479455B2
公开(公告)日：2009-01-20
申请号：US11157905
申请日：2005-06-22
申请人： Ki-Kwon Jeong , Hyeon Hwang
发明人： Ki-Kwon Jeong , Hyeon Hwang
IPC分类号： H01L21/302
CPC分类号： H01L21/6836 , H01L21/304 , H01L21/30625 , H01L2221/68327
摘要： A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.
摘要翻译：一种方法可包括使用粘合剂将第一支撑板安装在晶片的有效表面上。晶片背表面的一部分可能被重叠。可以使用粘合剂将第二支撑板安装在晶片的背面上。第一支撑板可以从晶片的有效表面移除。可以在活性表面上设置导电凸块。重叠过程可以包括第一研磨工艺，第二研磨工艺和抛光工艺。第一和第二支撑板可以由固体材料制成。粘合剂可以是紫外线固化粘合剂或热固化粘合剂。

6. 发明申请

US20060166462A1 Method for manufacturing semiconductor wafer 有权
公开(公告)号：US20060166462A1
公开(公告)日：2006-07-27
申请号：US11157905
申请日：2005-06-22
申请人： Ki-Kwon Jeong , Hyeon Hwang
发明人： Ki-Kwon Jeong , Hyeon Hwang
IPC分类号： H01L21/461
CPC分类号： H01L21/6836 , H01L21/304 , H01L21/30625 , H01L2221/68327
摘要： A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

7. 发明申请

US20060202332A1 Semiconductor chip packaging apparatus and method of manufacturing semiconductor chip package 审中-公开
标题翻译：半导体芯片封装装置及半导体芯片封装的制造方法
公开(公告)号：US20060202332A1
公开(公告)日：2006-09-14
申请号：US11418010
申请日：2006-05-05
申请人： Se-Young Jeong , Gi-Young Sohn , Ki-Kwon Jeong , Hyeon Hwang
发明人： Se-Young Jeong , Gi-Young Sohn , Ki-Kwon Jeong , Hyeon Hwang
IPC分类号： H01L23/48
CPC分类号： H01L21/4835 , H01L23/49582 , H01L2924/00014 , H01L2924/0002 , H01L2224/45099 , H01L2924/00
摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus includes a plating unit that is disposed in a direction to form a conductive plating layer on external terminals of the semiconductor chip package; and a reflow unit that is disposed with the plating unit to melt the conductive plating layer. The packaging apparatus may further include a rinsing unit that is disposed with the plating unit to clean and cool the conductive plating layer. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.
摘要翻译：公开了半导体芯片封装装置及其方法的示例性实施例。包装装置包括镀敷单元，该镀覆单元沿着在半导体芯片封装的外部端子上形成导电镀层的方向设置; 以及与所述电镀单元配置以熔化所述导电性镀层的回流单元。包装装置还可以包括与镀覆单元一起设置以清洁和冷却导电镀层的冲洗单元。因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

8. 发明申请

US20060019463A1 Die attaching method of semiconductor chip using warpage prevention material 有权
标题翻译：使用防翘曲材料制造半导体芯片的贴片方法
公开(公告)号：US20060019463A1
公开(公告)日：2006-01-26
申请号：US11045078
申请日：2005-01-31
申请人： Ki-kwon Jeong , Hyeon Hwang
发明人： Ki-kwon Jeong , Hyeon Hwang
IPC分类号： H01L21/44
CPC分类号： H01L21/78 , H01L21/6835 , H01L2221/68318 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368 , H01L2221/6839
摘要： A die attaching method of a semiconductor chip simplifies the process of fabricating a package from the chip while preventing the chip form being damaged even when the chip is very thin. Warpage prevention material is adhered to a top surface of a wafer having a plurality of chips formed thereon, and then the wafer is cut to separate the chips from one another. Each semiconductor chip is then placed on and attached to a die pad of a base frame, while the warpage prevention material is detached from the semiconductor chip. Thus, the warpage prevention material is removed without requiring a process that is extraneous to the die attaching process.
摘要翻译：半导体芯片的管芯附接方法简化了从芯片制造封装的过程，同时防止芯片形式受损，即使芯片非常薄。防翘曲材料附着在其上形成有多个芯片的晶片的顶表面上，然后切割晶片以将芯片彼此分离。然后将每个半导体芯片放置并附接到基架的芯片焊盘，同时防止翘曲材料与半导体芯片分离。因此，除去防翘曲材料，而不需要与模具附接工艺无关的工艺。

9. 发明申请

US20050153522A1 Wafer level chip stack method 失效
标题翻译：晶圆级芯片堆叠方式
公开(公告)号：US20050153522A1
公开(公告)日：2005-07-14
申请号：US10944002
申请日：2004-09-20
申请人： Hyeon Hwang , Dong-Kuk Kim , Ki-Kwon Jeong
发明人： Hyeon Hwang , Dong-Kuk Kim , Ki-Kwon Jeong
IPC分类号： H01L21/60 , H01L21/00 , H01L21/44 , H01L21/48 , H01L21/58 , H01L21/68 , H01L21/78 , H01L21/98 , H01L25/065
CPC分类号： H01L24/27 , H01L21/67132 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L24/29 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2221/68354 , H01L2221/68368 , H01L2224/274 , H01L2224/32145 , H01L2224/83001 , H01L2224/83191 , H01L2224/8385 , H01L2224/97 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/07802 , H01L2924/12042 , H01L2224/83 , H01L2924/00
摘要： Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.
摘要翻译：提供了可以在晶片级堆叠不同大小的芯片的方法。晶片级芯片堆叠方法利用在胶带上支撑第一和第二晶片的第一和第二晶片组件。支撑的晶片中的一个或两个可以锯切或以其他方式分割，以获得保持固定到相应的第一环形框架的分离的第一和第二芯片。然后可以将第一和第二晶片组件定位和对准，使得第二晶片的后表面面向第一晶片的有效表面。然后可以将每个第二芯片结合到相应的第一芯片以使用粘合剂层形成芯片堆叠。然后可以将芯片堆叠从晶片组件分离并附接到衬底。

10. 发明申请

US20080051055A1 Frequency conversion circuit 有权
标题翻译：变频电路
公开(公告)号：US20080051055A1
公开(公告)日：2008-02-28
申请号：US11878145
申请日：2007-07-20
申请人： Hyeon Hwang , Seung Oh
发明人： Hyeon Hwang , Seung Oh
IPC分类号： H04B1/26
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D2200/0033 , H03D2200/0047
摘要： A frequency conversion circuit comprises an input stage composed of one or more transistors, the input stage outputting a current corresponding to a voltage-type RF signal which is input to the gate of the transistor; a frequency conversion stage receiving an LO signal, causing the output RF signal to transit by the frequency of the LO signal so as to output an IF signal, and detecting an output voltage of the IF signal; a bleeding transistor connected to the input stage, supplying a current corresponding to a DC voltage, applied to a gate-source stage thereof, as a bleeding current to the transistor of the input stage, and in an AC manner, operating complementarily with the input stage to control a current flowing in the frequency conversion stage; a common mode feedback circuit comparing an output voltage provided from the frequency conversion stage with a preset reference voltage, adjusting the output voltage such that the output voltage is equalized to the reference voltage, and directly feeding the adjusted output voltage to the bleeding transistor; and a load stage composed of resistors and distributing a power supply voltage to apply to the frequency conversion stage.
摘要翻译：频率转换电路包括由一个或多个晶体管组成的输入级，输入级输出对应于输入到晶体管的栅极的电压型RF信号的电流; 频率转换级接收LO信号，使得输出RF信号通过LO信号的频率转移，以输出IF信号，并检测IF信号的输出电压; 连接到输入级的出血晶体管，将施加到其栅极 - 源极级的对应于直流电压的电流作为输出级的晶体管的输出电流提供，并以AC方式与输入端互补地工作控制在变频阶段流动的电流; 将从变频级提供的输出电压与预设参考电压进行比较的共模反馈电路，调整输出电压使得输出电压与参考电压相等，并将调整的输出电压直接馈送到出血晶体管; 以及由电阻器组成的负载级，并分配施加到变频级的电源电压。

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