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1. 发明申请

US20050025270A1 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US20050025270A1
公开(公告)日：2005-02-03
申请号：US10924303
申请日：2004-08-23
申请人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , H03D3/22
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

2. 发明申请

US20050025268A1 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
公开(公告)号：US20050025268A1
公开(公告)日：2005-02-03
申请号：US10924159
申请日：2004-08-23
申请人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , H03D1/24
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

3. 发明申请

US20050025269A1 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US20050025269A1
公开(公告)日：2005-02-03
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert Staszewski , Gennady Feygin
IPC分类号： H03D7/12 , H04B1/10 , H03D3/22
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

4. 发明申请

US20070103240A1 Gain Calibration of a Digital Controlled Oscillator 有权
标题翻译：数字控制振荡器的增益校准
公开(公告)号：US20070103240A1
公开(公告)日：2007-05-10
申请号：US11619529
申请日：2007-01-03
申请人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
发明人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

5. 发明申请

US20060033582A1 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US20060033582A1
公开(公告)日：2006-02-16
申请号：US11149859
申请日：2005-06-10
申请人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
发明人： Robert Staszewski , Gennady Feygin , Oren Eliezer , Dirk Leipold
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

6. 发明授权

US07623838B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US07623838B2
公开(公告)日：2009-11-24
申请号：US11028995
申请日：2005-01-03
申请人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

7. 发明申请

US20050186920A1 Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor 审中-公开
标题翻译：噪声抑制和抖动的装置和方法，以提高数字RF处理器中的分辨率质量
公开(公告)号：US20050186920A1
公开(公告)日：2005-08-25
申请号：US11062254
申请日：2005-02-18
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad , Sameh Rezeq
IPC分类号： H03C3/00 , H03L7/16 , H04B1/04 , H04B1/06 , H04B1/68
CPC分类号： H03L7/16 , H03L2207/50
摘要： A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.
摘要翻译：一种用于数字RF处理器（DRP）中的噪声和伪噪声抑制的新型装置和方法。本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。噪声抑制方案消除了通过电磁，电源，接地和基板路径传输的各种片上干扰源引起的噪声。噪声抑制方案允许所有数字PLL（ADPLL）以这样的方式操作，以避免产生通常由芯片上的干扰源的注入拉动效应产生的杂散。频率参考时钟重新定时与RF振荡器时钟同步，用于驱动DRP的整个数字逻辑电路。这确保了整个系统中不同的时钟沿不会出现相互漂移。还提出了一种提高ADPLL内数字转换器的分辨率质量的方法。该方法通过将参考时钟传递通过由Σ-Δ调制器控制的延迟电路来抖动参考时钟。由于TDC定时估计的不正确的量化，抖动参考时钟降低了对ADPLL输出的相位噪声的影响。

8. 发明申请

US20050036572A1 Method of rate conversion together with I-Q mismatch correction and sampler phase adjustment in direct sampling based down-conversion 审中-公开
标题翻译：速率转换方法与基于直接采样的下转换中的I-Q失配校正和采样器相位调整
公开(公告)号：US20050036572A1
公开(公告)日：2005-02-17
申请号：US10641235
申请日：2003-08-14
申请人： Khurram Muhammad , Robert Staszewski , Imtinan Elahi
发明人： Khurram Muhammad , Robert Staszewski , Imtinan Elahi
IPC分类号： H04B1/30 , H04L7/02 , H04L27/06
CPC分类号： H04L7/0029 , H04B1/30 , H04L7/007
摘要： A method of digital resampling converts a channel dependent rate to a fixed rate while correcting gain and phase mismatch between I and Q branches in the resampling process and adjusts the sampler phase for T-spaced equalization.
摘要翻译：数字重采样的方法将信道相关速率转换为固定速率，同时校正重采样过程中I和Q分支之间的增益和相位失配，并调整采样器相位进行T间隔均衡。

9. 发明申请

US20060164160A1 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US20060164160A1
公开(公告)日：2006-07-27
申请号：US11388558
申请日：2006-03-24
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

10. 发明申请

US20060290435A1 Type-II All-Digital Phase-Locked Loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US20060290435A1
公开(公告)日：2006-12-28
申请号：US11464420
申请日：2006-08-14
申请人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

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