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1. 发明授权

US07397263B2 Sensor differentiated fault isolation 有权
标题翻译：传感器差分故障隔离
公开(公告)号：US07397263B2
公开(公告)日：2008-07-08
申请号：US11670001
申请日：2007-02-01
申请人： Kevin L. Condon , Theodore M. Levin , Leah M. Pastel , David P. Vallett
发明人： Kevin L. Condon , Theodore M. Levin , Leah M. Pastel , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译：公开了一种用于诊断测试设备内的电路的装置和方法。该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个响应。本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。相关器被配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性能源的位置和传感器的位置。

2. 发明授权

US07202689B2 Sensor differentiated fault isolation 失效
标题翻译：传感器差分故障隔离
公开(公告)号：US07202689B2
公开(公告)日：2007-04-10
申请号：US10907787
申请日：2005-04-15
申请人： Kevin L. Condon , Theodore M. Levin , Leah M. P. Pastel , David P. Vallett
发明人： Kevin L. Condon , Theodore M. Levin , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译：公开了一种用于诊断测试设备内的电路的装置和方法。该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个响应。本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。相关器配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性能源的位置和传感器的位置。

3. 发明授权

US07230335B2 Inspection methods and structures for visualizing and/or detecting specific chip structures 有权
标题翻译：用于可视化和/或检测特定芯片结构的检查方法和结构
公开(公告)号：US07230335B2
公开(公告)日：2007-06-12
申请号：US10711765
申请日：2004-10-04
申请人： Jerome L. Cann , Steven J. Holmes , Leendert M. Huisman , Cherie R. Kagan , Leah M. Pastel , Paul W. Pastel , James R. Salimeno, III , David P. Vallett
发明人： Jerome L. Cann , Steven J. Holmes , Leendert M. Huisman , Cherie R. Kagan , Leah M. Pastel , Paul W. Pastel , James R. Salimeno, III , David P. Vallett
IPC分类号： H01L23/48 , H01L21/302
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76843 , H01L21/76865 , H01L21/7688
摘要： The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.
摘要翻译：本发明提供了用于促进特定芯片结构的可视化和/或检测的检查方法和结构。光学或荧光标记技术用于“污染”特定的芯片结构，以便于检测结构。此外，向半导体工艺中添加临时/牺牲照明（例如荧光）膜以便于检测特定的芯片结构。此外，在半导体工艺期间，用荧光材料掺杂特定的芯片结构。本发明的方法包括：提供第一和第二材料; 处理所述第一材料以形成半导体结构的一部分; 以及检测所述第二材料的状态以确定所述第一材料的处理是否完成。

4. 发明授权

US07671604B2 Nanoscale fault isolation and measurement system 失效
标题翻译：纳米级故障隔离测量系统
公开(公告)号：US07671604B2
公开(公告)日：2010-03-02
申请号：US12116497
申请日：2008-05-07
申请人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
发明人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
IPC分类号： H01H31/02 , G01R27/08 , G01R31/02
CPC分类号： G01R1/06705 , G01R1/0466 , G01R31/2844 , G01R31/2886
摘要： Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
摘要翻译：公开了一种在公共平台上提供多个近场扫描隔离技术的故障隔离和测量系统。该系统包括使用专门的保持器来为位于设备或材料的区域内的内部电路结构提供电偏压。该系统还使用多探头组件。每个探头安装在围绕公共参考点的支撑结构上，并且是不同测量或故障隔离工具的组件。组件移动使得每个探针可以从设备或材料上的相同固定位置获得测量值。可以改变支撑结构和/或保持器的相对定位，以便从区域内的多个相同的固定位置获得测量值。此外，该系统使用处理器来提供与每个信号相关联的分层图像，并且用于将这些图像与设计数据精确对准，以便表征或隔离设备或材料内的故障位置。

5. 发明申请

US20080238457A1 NANOSCALE FAULT ISOLATION AND MEASUREMENT SYSTEM 失效
标题翻译： NANOSCALE故障分离和测量系统
公开(公告)号：US20080238457A1
公开(公告)日：2008-10-02
申请号：US12116497
申请日：2008-05-07
申请人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
发明人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
IPC分类号： G01R31/28 , G06K9/00
CPC分类号： G01R1/06705 , G01R1/0466 , G01R31/2844 , G01R31/2886
摘要： Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
摘要翻译：公开了一种在公共平台上提供多个近场扫描隔离技术的故障隔离和测量系统。该系统包括使用专门的保持器来为位于设备或材料的区域内的内部电路结构提供电偏压。该系统还使用多探头组件。每个探头安装在围绕公共参考点的支撑结构上，并且是不同测量或故障隔离工具的组件。组件移动使得每个探针可以从设备或材料上的相同固定位置获得测量值。可以改变支撑结构和/或保持器的相对定位，以便从区域内的多个相同的固定位置获得测量值。此外，该系统使用处理器来提供与每个信号相关联的分层图像，并且用于将这些图像与设计数据精确对准，以便表征或隔离设备或材料内的故障位置。

6. 发明授权

US07116094B2 Apparatus and method for transmission and remote sensing of signals from integrated circuit devices 失效
标题翻译：用于从集成电路器件传输和遥感信号的装置和方法
公开(公告)号：US07116094B2
公开(公告)日：2006-10-03
申请号：US10710683
申请日：2004-07-28
申请人： Theodore M. Levin , David P. Vallett
发明人： Theodore M. Levin , David P. Vallett
IPC分类号： G01R15/20 , G01R1/20 , G01R15/18 , G01R33/02
CPC分类号： G01R31/2886 , G01R15/20 , G01R31/3004 , G01R31/3025
摘要： An apparatus and a method for testing semiconductor devices, such as individual integrated circuits in semiconductor chips, by directing a current in each circuit through a respective selected predetermined path to establish, in each circuit, a respective focused magnetic field and converting each such magnetic field into a respective voltage which, when fed to respective amplifier gated with a respective selected frequency, will modulate each such respective voltage. Each such respective voltage is then used to create a respective pulsating magnetic field that when detected by a respective remote magnetic sensor will provide a series of respective signals representative of the current in the respective circuit from which the pulsating magnetic field was derived. By applying each such series of voltages to a lock-in amplifier synchronized at the respective frequencies gating each respective amplifier the current in each circuit being tested can be accurately determined and will be free of errors due to circuit noise or crosstalk between the circuits under test.
摘要翻译：一种用于测试半导体芯片中的各个集成电路的半导体器件的装置和方法，通过在每个电路中引导电流通过相应的选定的预定路径，以在每个电路中建立相应的聚焦磁场并将每个这样的磁场当被馈送到以相应选定频率门控的相应放大器时，将调制每个这样的相应电压。然后使用每个这样的各个电压来产生相应的脉动磁场，当相应的远程磁传感器检测到时，将提供一系列相应的信号，该信号表示从其产生脉动磁场的相应电路中的电流。通过将每个这样的一系列电压施加到锁定放大器，该锁定放大器在各自的频率上同步，门控各个放大器，可以精确地确定正在测试的每个电路中的电流，并且将由于被测电路之间的电路噪声或串扰而没有错误。

7. 发明授权

US07511510B2 Nanoscale fault isolation and measurement system 有权
标题翻译：纳米级故障隔离测量系统
公开(公告)号：US07511510B2
公开(公告)日：2009-03-31
申请号：US11164654
申请日：2005-11-30
申请人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
发明人： Philip V. Kaszuba , Theodore M. Levin , David P. Vallett
IPC分类号： H01H31/02 , G01R27/08 , G01R31/02
CPC分类号： G01R1/06705 , G01R1/0466 , G01R31/2844 , G01R31/2886
摘要： Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.
摘要翻译：公开了一种在公共平台上提供多个近场扫描隔离技术的故障隔离和测量系统。该系统包括使用专门的保持器来为位于设备或材料的区域内的内部电路结构提供电偏压。该系统还使用多探头组件。每个探头安装在围绕公共参考点的支撑结构上，并且是不同测量或故障隔离工具的组件。组件移动使得每个探针可以从设备或材料上的相同固定位置获得测量值。可以改变支撑结构和/或保持器的相对定位，以便从区域内的多个相同的固定位置获得测量值。此外，该系统使用处理器来提供与每个信号相关联的分层图像，并且用于将这些图像与设计数据精确对准，以便表征或隔离设备或材料内的故障位置。

8. 发明授权

US07247877B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07247877B2
公开(公告)日：2007-07-24
申请号：US10711083
申请日：2004-08-20
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： H01L31/072 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

9. 发明授权

US07005874B2 Utilizing clock shield as defect monitor 有权
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07005874B2
公开(公告)日：2006-02-28
申请号：US10710222
申请日：2004-06-28
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

10. 发明授权

US06452209B2 Semiconductor devices having backside probing capability 失效
标题翻译：具有背面探测能力的半导体器件
公开(公告)号：US06452209B2
公开(公告)日：2002-09-17
申请号：US09771778
申请日：2001-01-29
申请人： David P. Vallett
发明人： David P. Vallett
IPC分类号： H01L2358
CPC分类号： H01L22/32 , G01R31/2884
摘要： Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.
摘要翻译：提供集成电路，其允许在操作时进行背面探测。导电沟槽在预选位置被制成半导体芯片的表面。通过半导体芯片的背面变薄和铣削，然后通过电子束探头或机械探针使用，可以通过导电沟槽实现对集成电路的特定电连接节点的访问。

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