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1. 发明授权

US09207958B1 Virtual machine coprocessor for accelerating software execution 有权
标题翻译：用于加速软件执行的虚拟机协处理器
公开(公告)号：US09207958B1
公开(公告)日：2015-12-08
申请号：US10637005
申请日：2003-08-08
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F9/45516 , G06F9/3836 , G06F9/455
摘要： In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor.
摘要翻译：在一个一般方面，系统包括抽象机器指令流，虚拟机协处理器，被配置为从抽象机器指令流接收指令，并响应于接收到的指令生成一个或多个本机机器指令;以及处理器，该虚拟机协处理器可操作以执行虚拟机协处理器生成的本地机器指令。虚拟机协处理器可操作地生成一个或多个本地机器指令以明确地控制虚拟机协处理器。

2. 发明授权

US07849297B2 Software emulation of directed exceptions in a multithreading processor 有权
标题翻译：多线程处理器中的定向异常的软件仿真
公开(公告)号：US07849297B2
公开(公告)日：2010-12-07
申请号：US11313272
申请日：2005-12-20
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/445 , G06F9/455
CPC分类号： G06F9/4812 , G06F9/4881
摘要： A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception—including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.
摘要翻译：多线程微处理器具有多个线程上下文（TC），每个线程上下文（TC）各自包括足够的状态，诸如通用寄存器和程序计数器，以执行单独的执行线程作为由多处理器操作系统控制的多个对称处理器之一。然而，微处理器硬件不支持一个TC将异常引导到另一个TC的能力，即指定异常指向的其他TC中的哪一个。在操作系统的第一TC上运行的第一个线程执行架构化指令以停止在第二TC上运行的第二个线程（用户或内核线程），保存第二TC的状态，写入第二TC状态以模拟异常 - 包括使用异常处理程序的地址写入重新启动寄存器，并取消第二个TC执行异常处理程序。

3. 发明授权

US07747989B1 Virtual machine coprocessor facilitating dynamic compilation 有权
标题翻译：虚拟机协处理器促进动态编译
公开(公告)号：US07747989B1
公开(公告)日：2010-06-29
申请号：US10637006
申请日：2003-08-08
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F9/45516 , G06F9/3836 , G06F9/455
摘要： A system includes an abstract machine instruction stream, an execution trace buffer storing information to facilitate dynamic compilation, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor updates the execution trace buffer as instructions from the abstract machine instruction stream are processed. In addition, a method for facilitating dynamic compilation includes receiving an instruction to be processed, determining that the instruction marks entry into a basic block, and updating an execution trace buffer.
摘要翻译：系统包括抽象机器指令流，存储用于促进动态编译的信息的执行跟踪缓冲器，配置成从抽象机器指令流接收指令并响应于接收到的指令生成一个或多个本地机器指令的虚拟机协处理器以及处理器，其耦合到所述虚拟机协处理器并且可操作以执行由所述虚拟机协处理器生成的本地机器指令。当处理来自抽象机器指令流的指令时，虚拟机协处理器更新执行跟踪缓冲器。此外，用于促进动态编译的方法包括接收待处理的指令，确定指令标记进入基本块，以及更新执行跟踪缓冲器。

4. 发明申请

US20090198986A1 Configurable Instruction Sequence Generation 有权
标题翻译：可配置指令序列生成
公开(公告)号：US20090198986A1
公开(公告)日：2009-08-06
申请号：US12399330
申请日：2009-03-06
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30167 , G06F9/30181
摘要： A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.
摘要翻译：提供了可配置的指令集架构，由此可以使用单个虚拟指令来生成指令序列。动态参数替换可用于将由虚拟指令指定的参数替换为虚拟指令序列内的指令。

5. 发明申请

US20080140998A1 INTEGRATED MECHANISM FOR SUSPENSION AND DEALLOCATION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR 有权
标题翻译：综合机构暂停执行处理器执行计算螺纹
公开(公告)号：US20080140998A1
公开(公告)日：2008-06-12
申请号：US11949603
申请日：2007-12-03
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/30
CPC分类号： G06F9/3009 , G06F8/4442 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4881 , G06F9/54
摘要： A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input operand specifies one or more of the independently occurring events. The yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of the independently occurring events specified by the input operand has occurred. The program thread contains the yield instruction. The yield instruction further instructs the microprocessor core to return a value in the output operand indicating which of the independently occurring events occurred to cause the microprocessor core to resume issuing the instructions of the program thread.
摘要翻译：微处理器核心包括指示是否已经发生相应的多个独立发生的事件的多个输入。输入是非内存地址输入。核心还包括其指令集架构中的产出指令，包括用户可见的输出操作数和显式输入操作数。输入操作数指定一个或多个独立发生的事件。产出指令指示微处理器核心暂停执行程序线程的执行指令，直到发生由输入操作数指定的至少一个独立发生的事件。程序线程包含yield指令。产出指令进一步指示微处理器核心返回输出操作数中的值，指示发生哪些独立发生的事件，以使微处理器核心恢复发出程序线程的指令。

6. 发明授权

US09552293B1 Emulating eviction data paths for invalidated instruction cache 有权
标题翻译：仿真无效指令缓存的驱逐数据路径
公开(公告)号：US09552293B1
公开(公告)日：2017-01-24
申请号：US13567206
申请日：2012-08-06
申请人： Benjamin Charles Serebrin , David Levinthal , Kevin D. Kissell , Clinton Wills Smullen, IV
发明人： Benjamin Charles Serebrin , David Levinthal , Kevin D. Kissell , Clinton Wills Smullen, IV
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0802 , G06F12/0808 , G06F12/0811 , G06F12/0862 , G06F2212/1041
摘要： A method of managing processor caches. The method includes invalidating a cache line from a first instruction cache level and in response to invalidating the cache line from the first cache level, fetching data associated with the invalidated cache line from a third cache level or memory and writing the fetched data to a second cache level. The third cache level is larger or differently associative than the second cache level and the second cache level is larger or differently associative than the first cache level.
摘要翻译：管理处理器高速缓存的方法。该方法包括从第一指令高速缓存级别使高速缓存行无效，并且响应于从第一高速缓存级别使高速缓存行无效，从第三高速缓存级别或存储器获取与无效高速缓存行相关联的数据，并将获取的数据写入第二高速缓存缓存级别。第三高速缓存级别比第二高速缓存级别更大或不同地相关联，并且第二高速缓存级别比第一高速缓存级别更大或不同地相关联。

7. 发明授权

US09032404B2 Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor 有权
标题翻译：在多线程处理器中使用定向异常的软件仿真的抢占式多任务
公开(公告)号：US09032404B2
公开(公告)日：2015-05-12
申请号：US11313296
申请日：2005-12-20
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/46 , G06F9/30 , G06F9/45 , G06F9/48
CPC分类号： G06F9/3017 , G06F8/4442 , G06F9/30032 , G06F9/30123 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3851 , G06F9/4812 , G06F9/4881
摘要： A multiprocessor computer system includes an exception domain having multiple thread contexts (TCs) each having a restart address register, and a timer that generates a periodic interrupt request to the exception domain. The exception domain selects an eligible TC to service the interrupt request, which is non-specific regarding which TC to select. A first interrupt handler executes on the selected TC to service the interrupt request to schedule a set of processes assigned by the SMP OS for execution on the selected TC, and write an address of a second interrupt handler to the restart address register of each TC other than the selected TC. The second interrupt handler schedules a plurality of sets of processes assigned by the SMP OS for execution on respective ones of the TCs other than the selected TC.
摘要翻译：多处理器计算机系统包括具有多个具有重新启动地址寄存器的多个线程上下文（TC）的异常域和产生对异常域的周期性中断请求的定时器。异常域选择合格的TC来服务中断请求，这对于要选择哪个TC是非特定的。第一个中断处理程序在所选择的TC上执行以服务中断请求，以调度由SMP OS分配的用于在所选择的TC上执行的一组进程，并将第二个中断处理程序的地址写入每个TC其他的重新启动地址寄存器比选择的TC。第二中断处理程序调度由SMP OS分配的多个进程集合，用于在除所选择的TC之外的各个TC上执行。

8. 发明授权

US07870553B2 Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts 有权
标题翻译：对称多处理器操作系统，用于在非独立轻量级线程上下文中执行
公开(公告)号：US07870553B2
公开(公告)日：2011-01-11
申请号：US11330916
申请日：2006-01-11
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/4812 , G06F9/4881 , Y02D10/24
摘要： A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.
摘要翻译：公开了一种多处理系统。该系统包括具有多个线程上下文（TC）的多线程微处理器，由多个TC共享的转换后备缓冲器（TLB），以及指令调度器，被配置为分配到执行单元多线程方式，在多个TC上执行的线程的指令。所述系统还包括多处理器操作系统（OS），其被配置为调度所述多个TC上的线程的执行，其中在所述多个TC之一上执行的线程的线程被配置为更新所述共享TLB，并且在更新所述TLB以禁止中断，以防止所述OS使所述TLB更新线程在所述多个TC上不执行，并且禁止所述指令调度器从所述多个TC中的所述TC之外的所述多个TC中的任一个发送指令， TLB更新线程正在其上执行。

9. 发明授权

US07836450B2 Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts 有权
标题翻译：对称多处理器操作系统，用于在非独立轻量级线程上下文中执行
公开(公告)号：US07836450B2
公开(公告)日：2010-11-16
申请号：US11330915
申请日：2006-01-11
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F9/3851 , G06F9/4812 , G06F9/4881 , Y02D10/24
摘要： A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.
摘要翻译：公开了一种多处理系统。该系统包括多线程微处理器，包括多个线程上下文（TC），每个线程上下文（TC）包括用于控制TC是否免除服务于多个TC的异常域的中断请求的第一控制指示符，以及虚拟处理元件 VPE），其包括异常域，被配置为接收中断请求，其中所述中断请求对于所述多个TC是非特定的，其中所述VPE被配置为选择所述多个TC中的非免除的一个以服务于所述中断请求，所述VPE还包括用于控制所述VPE是否能够选择所述多个TC中的一个以服务所述中断请求的第二控制指示符。所述系统还包括多处理器操作系统（OS），其被配置为初始设置所述第二控制指示符以使得所述VPE能够服务所述中断，并且还被配置为调度所述多个TC上的线程的执行，其中，所述线程中的每一个被配置通过设置第一个控制指示灯，而不是通过清除第二个控制指示灯来单独禁止自己维护中断。

10. 发明授权

US07725697B2 Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts 有权
标题翻译：对称多处理器操作系统，用于在非独立轻量级线程上下文中执行
公开(公告)号：US07725697B2
公开(公告)日：2010-05-25
申请号：US11615963
申请日：2006-12-23
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30043 , G06F9/3009 , G06F9/30101 , G06F9/455 , G06F9/4812 , G06F9/4881 , Y02D10/24
摘要： a multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs) configured as an array, each having a program counter, a general purpose register set for executing a thread, and a register for storing an index of the respective TC within the array. The OS maintains a table of entries, each the entry for storing a CPU-unique value for a respective one of the TCs. The OS comprises a respective thread configured to execute on each of the respective TCs and to read the index from the register of the respective one of the TCs and to read the respective CPU-unique value for the respective one of the TCs using the index.
摘要翻译：公开了一种包括多线程微处理器和多处理器操作系统（OS）的多处理系统。微处理器包括配置为阵列的多个线程上下文（TC），每个线程上下文（TC）具有程序计数器，用于执行线程的通用寄存器集，以及用于存储阵列内各个TC的索引的寄存器。 OS维护条目表，每个条目用于存储相应一个TC的CPU唯一值。 OS包括被配置为在相应TC中的每一个上执行并且从TC的相应一个的寄存器读取索引并且使用该索引读取相应的一个TC的相应CPU唯一值的相应线程。

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