专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08975525B2 Corles multi-layer circuit substrate with minimized pad capacitance 有权
标题翻译：具有最小焊盘电容的Corles多层电路基板
公开(公告)号：US08975525B2
公开(公告)日：2015-03-10
申请号：US13614314
申请日：2012-09-13
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC分类号： H05K1/00 , H05K1/02 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
摘要翻译：多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。在金属层之间放置两种不同类型的绝缘层。这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

2. 发明申请

US20130008696A1 CORLES MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE 有权
标题翻译：具有最小化焊盘电容的多层电路基板
公开(公告)号：US20130008696A1
公开(公告)日：2013-01-10
申请号：US13614314
申请日：2012-09-13
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC分类号： H05K1/00
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
摘要翻译：多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。在金属层之间放置两种不同类型的绝缘层。这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

3. 发明申请

US20130003335A1 CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE 审中-公开
标题翻译：具有最小化焊盘电容的无线多层电路基板
公开(公告)号：US20130003335A1
公开(公告)日：2013-01-03
申请号：US13612459
申请日：2012-09-12
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC分类号： H05K7/06
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
摘要翻译：多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。在金属层之间放置两种不同类型的绝缘层。这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

4. 发明授权

US08389870B2 Coreless multi-layer circuit substrate with minimized pad capacitance 有权
公开(公告)号：US08389870B2
公开(公告)日：2013-03-05
申请号：US12720386
申请日：2010-03-09
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC分类号： H05K1/11
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

5. 发明申请

US20110222224A1 CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE 有权
标题翻译：具有最小化焊盘电容的无线多层电路基板
公开(公告)号：US20110222224A1
公开(公告)日：2011-09-15
申请号：US12720386
申请日：2010-03-09
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Hong Kim , Rohan Mandrekar
IPC分类号： G06F1/16 , H05K1/11 , H05K1/00 , H05K7/00
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
摘要翻译：多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。在金属层之间放置两种不同类型的绝缘层。这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

6. 发明授权

US09060428B2 Coreless multi-layer circuit substrate with minimized pad capacitance 有权
标题翻译：具有最小焊盘电容的无芯多层电路基板
公开(公告)号：US09060428B2
公开(公告)日：2015-06-16
申请号：US13612459
申请日：2012-09-12
申请人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Tong Kim , Rohan Mandrekar
发明人： Kevin Bills , Mahesh Bohra , Jinwoo Choi , Tae Tong Kim , Rohan Mandrekar
IPC分类号： H05K1/16 , H05K1/02 , H01L23/498 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L2224/16 , H01L2224/16235 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H05K1/0231 , H05K1/024 , H05K1/0251 , H05K1/113 , H05K1/144 , H05K2201/0187 , H05K2201/041 , H05K2201/09481 , H05K2201/09718 , H05K2201/10734 , Y10T29/49124 , Y10T29/49151 , H01L2924/00
摘要： A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
摘要翻译：多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。在金属层之间放置两种不同类型的绝缘层。这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

7. 发明授权

US08358509B2 Reduced wiring requirements with signal slope manipulation 失效
标题翻译：信号斜率控制降低布线要求
公开(公告)号：US08358509B2
公开(公告)日：2013-01-22
申请号：US12362649
申请日：2009-01-30
申请人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
发明人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
IPC分类号： H05K3/00
CPC分类号： H04B1/04 , H03M3/024
摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.
摘要翻译：信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路和多个电子部件的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号利用斜率操作来传输，以提供与数据值。

8. 发明授权

US08743558B2 Reduced wiring requirements with signal slope manipulation 失效
标题翻译：信号斜率控制降低布线要求
公开(公告)号：US08743558B2
公开(公告)日：2014-06-03
申请号：US13614119
申请日：2012-09-13
申请人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
发明人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
IPC分类号： H05K7/00
CPC分类号： H04B1/04 , H03M3/024
摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.
摘要翻译：信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号中的每一个通过操纵所述至少一个电信号中的每个电信号而利用斜率操作传输，以提供基本上与n个离散整数数据值的离散整数数据值成比例的斜率，n是大于或等于3的正整数，所述离散整数数据值使用n个不同斜率之一表示，所述斜率使用n的特定参考电压预定参考电压。

9. 发明申请

US20130010445A1 REDUCED WIRING REQUIREMENTS WITH SIGNAL SLOPE MANIPULATION 失效
标题翻译：具有信号斜率控制的降低接线要求
公开(公告)号：US20130010445A1
公开(公告)日：2013-01-10
申请号：US13614119
申请日：2012-09-13
申请人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
发明人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
IPC分类号： H05K7/00
CPC分类号： H04B1/04 , H03M3/024
摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.
摘要翻译：信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号中的每一个通过操纵所述至少一个电信号中的每个电信号而利用斜率操作传输，以提供基本上与n个离散整数数据值的离散整数数据值成比例的斜率，n是大于或等于3的正整数，所述离散整数数据值使用n个不同斜率之一表示，所述斜率使用n的特定参考电压预定参考电压。

10. 发明申请

US20100195756A1 REDUCED WIRING REQUIREMENTS WITH SIGNAL SLOPE MANIPULATION 失效
标题翻译：具有信号斜率控制的降低接线要求
公开(公告)号：US20100195756A1
公开(公告)日：2010-08-05
申请号：US12362649
申请日：2009-01-30
申请人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
发明人： Kevin J. Bills , Mahesh Bohra , Jinwoo Choi , Lloyd A. Walls
IPC分类号： H04L27/00
CPC分类号： H04B1/04 , H03M3/024
摘要： An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit and the plurality of electronic components, wherein the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation to provide a slope directly proportional to a data value.
摘要翻译：信息处理系统装置包括多个电子部件; 电路，包括用于连接所述多个电子部件中的两个或更多个的至少一个迹线，以及经由至少一个电信号在所述多个电子部件之间传输数据; 以及包括用作电路和多个电子部件的基底的绝缘材料的基板，其中在所述多个电子部件之间传输的所述至少一个电信号利用斜率操作来传输，以提供与数据值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式