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1. 发明授权

US08230659B2 Intumescent fire door edge system 有权
标题翻译：膨胀防火门边缘系统
公开(公告)号：US08230659B2
公开(公告)日：2012-07-31
申请号：US12889867
申请日：2010-09-24
申请人： Kevin B. Langille , Dat T. Nguyen , Ho T. Nguyen , An Cong Bach
发明人： Kevin B. Langille , Dat T. Nguyen , Ho T. Nguyen , An Cong Bach
IPC分类号： E04C2/00 , E06B1/04
CPC分类号： E06B5/164 , B32B3/266 , B32B7/08 , B32B7/12 , B32B27/06 , B32B27/20 , B32B2264/108 , B32B2307/304 , B32B2307/3065 , B32B2307/50 , B32B2307/7242 , B32B2307/732 , B32B2419/00 , E06B5/161 , E06B2003/7082 , Y10T428/24331 , Y10T428/249923 , Y10T428/31942
摘要： An intumescent strip includes a first material layer and an opposing second material layer. A third material layer, formed from an intumescent material, is positioned between the first and second layers. The intumescent material includes a combination of intumescent particles suspended within a thermoplastic material. The intumescent particles have an activation temperature and are expandable when exposed to temperatures above the activation temperature. The thermoplastic material has a melting temperature that is lower than the activation temperature.
摘要翻译：膨胀条包括第一材料层和相对的第二材料层。由膨胀材料形成的第三材料层位于第一和第二层之间。膨胀材料包括悬浮在热塑性材料中的膨胀颗粒的组合。膨胀颗粒具有活化温度，并且当暴露于高于活化温度的温度时可膨胀。热塑性材料的熔融温度低于活化温度。

2. 发明申请

US20110314755A1 INTUMESCENT FIRE DOOR EDGE SYSTEM 有权
标题翻译： INTUMESCENT防火门边缘系统
公开(公告)号：US20110314755A1
公开(公告)日：2011-12-29
申请号：US12889867
申请日：2010-09-24
申请人： Kevin B. Langille , Dat T. Nguyen , Ho T. Nguyen , An Cong Bach
发明人： Kevin B. Langille , Dat T. Nguyen , Ho T. Nguyen , An Cong Bach
IPC分类号： E04B1/94 , B32B7/08 , B32B7/04 , E06B5/16 , E04C2/02
CPC分类号： E06B5/164 , B32B3/266 , B32B7/08 , B32B7/12 , B32B27/06 , B32B27/20 , B32B2264/108 , B32B2307/304 , B32B2307/3065 , B32B2307/50 , B32B2307/7242 , B32B2307/732 , B32B2419/00 , E06B5/161 , E06B2003/7082 , Y10T428/24331 , Y10T428/249923 , Y10T428/31942
摘要： An intumescent strip includes a first material layer and an opposing second material layer. A third material layer, formed from an intumescent material, is positioned between the first and second layers. The intumescent material includes a combination of intumescent particles suspended within a thermoplastic material. The intumescent particles have an activation temperature and are expandable when exposed to temperatures above the activation temperature. The thermoplastic material has a melting temperature that is lower than the activation temperature.
摘要翻译：膨胀条包括第一材料层和相对的第二材料层。由膨胀材料形成的第三材料层位于第一和第二层之间。膨胀材料包括悬浮在热塑性材料中的膨胀颗粒的组合。膨胀颗粒具有活化温度，并且当暴露于高于活化温度的温度时可膨胀。热塑性材料的熔融温度低于活化温度。

3. 发明授权

US06833286B2 Semiconductor device with variable pin locations 有权
标题翻译：具有可变引脚位置的半导体器件
公开(公告)号：US06833286B2
公开(公告)日：2004-12-21
申请号：US10218783
申请日：2002-08-14
申请人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
发明人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
IPC分类号： H01L2144
CPC分类号： G11C5/066 , G11C29/1201
摘要： An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.
摘要翻译：一种包括逻辑电路，多个引脚和将逻辑电路耦合到多个引脚的接口单元的半导体器件，其中接口单元允许任何引脚耦合到逻辑电路的任何部分。半导体器件提供了一种模板，通过该模板可以制造具有不同引脚分配的许多不同类型的半导体器件，而不需要改变生产掩模。

4. 发明授权

US6020755A Hybrid programmable gate arrays 失效
标题翻译：混合可编程门阵列
公开(公告)号：US6020755A
公开(公告)日：2000-02-01
申请号：US938550
申请日：1997-09-26
申请人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
发明人： William B. Andrews , Barry K. Britton , Thomas J. Hickey , Ronald T. Modo , Ho T. Nguyen , Lorraine L. Schadt , Satwant Singh
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17796 , H03K19/17732
摘要： A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array (FPGA) logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the pads, between the PLC array and the ASB, and between the ASB and the pad ring. Muxes in the FISH cells can be programmed to cause the FISH cells to operate either (1) as programmable interface cells (PICs) that provide a direct interface between the PLC array and the pad ring or (2) as ASB-interface cells (AICs) that (a) provide interfaces between the PLC array and the ASB and (b) control interfaces between the ASB and the pad ring.
摘要翻译：具有用于实现永久功能的一个或多个屏蔽编程设备（MPD）逻辑区域的单个集成电路（IC）和用于实现用户指定功能的现场可编程门阵列（FPGA）逻辑的一个或多个区域。 FPGA型逻辑提供编程灵活性，而MPD型逻辑提供了大小，速度，功能和美元成本优势。在一个实施例中，混合IC具有使用FPGA类型逻辑实现的可编程逻辑单元阵列（PLC）阵列，使用MPD型逻辑实现的特定应用块（ASB）和一个垫环阵列。快速接口交换层次（FISH）单元提供PLC阵列与PLC之间，PLC阵列与ASB之间以及ASB与焊盘环之间的接口。可以对FISH单元中的复用器进行编程，以使FISH单元（1）作为可编程接口单元（PIC）来操作，这些可编程接口单元（PIC）可在PLC阵列和焊盘环之间提供直接接口，或（2）作为ASB接口单元（AIC））（a）提供PLC阵列和ASB之间的接口，（b）控制ASB和焊盘环之间的接口。

5. 发明授权

US6124732A Signaling voltage range discriminator 失效
标题翻译：信号电压范围鉴别器
公开(公告)号：US6124732A
公开(公告)日：2000-09-26
申请号：US115683
申请日：1998-07-15
申请人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
发明人： Zeljko Zilic , Ho T. Nguyen , Gary P. Powell , William B. Andrews , Richard G. Stuby, Jr.
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585
摘要： The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.
摘要翻译：本发明提供了一种输入/输出（I / O）信令电压范围鉴别器（和相应的方法），其用于响应于检测到的信号电压来控制可配置逻辑器件，例如第二电子电路中的可配置I / O缓冲器第一电子电路的范围。鉴别器将第一电子电路的信号电压范围的指示输出到可配置的I / O缓冲器，使其能够适应第一电子电路使用的信号电平。然后，基于鉴别器提供的指示，I / O缓冲器可以将它的逻辑配置成容忍和/或与传送到第一电子电路的数字信号兼容。

6. 发明授权

US06465884B1 Semiconductor device with variable pin locations 有权
标题翻译：具有可变引脚位置的半导体器件
公开(公告)号：US06465884B1
公开(公告)日：2002-10-15
申请号：US09578082
申请日：2000-05-24
申请人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
发明人： Frederick H. Fischer , Kenneth D. Fitch , Ho T. Nguyen , Scott A. Segan
IPC分类号： H01L2940
CPC分类号： G11C5/066 , G11C29/1201
摘要： An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.
摘要翻译：一种包括逻辑电路，多个引脚和将逻辑电路耦合到多个引脚的接口单元的半导体器件，其中接口单元允许任何引脚耦合到逻辑电路的任何部分。半导体器件提供了一种模板，通过该模板可以制造具有不同引脚分配的许多不同类型的半导体器件，而不需要改变生产掩模。

7. 发明授权

US5986471A Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的双向缓冲器和补充逻辑和互连单元
公开(公告)号：US5986471A
公开(公告)日：1999-11-16
申请号：US950446
申请日：1997-10-15
申请人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： Barry K. Britton , Kai-Kit Ngai , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H03K19/173 , H03K19/00 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/1736
摘要： The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.
摘要翻译：双向（BI-DI）缓冲器和补充逻辑和互连（SLIC）单元被设计为被编程为以不同的模式操作，以便实现不同种类的逻辑电路。特别地，本发明的BI-DI缓冲器支持至少五种不同的操作模式。在第一种模式（模式A）中，BI-DI缓冲区为任何输入值产生逻辑“1”输出。在第二种模式（模式B）中，BI-DI缓冲区为任何输入值产生逻辑“0”输出。在第三种模式（模式C）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的输出信号。在第四模式（模式D）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的反相的输出信号。在第五模式（模式E）中，BI-DI缓冲器作为常规三态驱动器工作。可以将两个或更多个BI-DI缓冲器配置成形成具有两个或更多个输入的更复杂的逻辑电路。例如，BI-DI缓冲器的组可以被配置为作为FPGA的基本逻辑单元的一部分的SLIC单元。当在FPGA中使用时，BI-DI缓冲器和SLIC单元使得不同类型的逻辑电路的实现比传统FPGA更为有效，包括具有大量输入的解码器和状态机的逻辑电路。同时，FPGA保留了实现FPGA传统上非常有效的逻辑电路的效率，例如随机逻辑和数据通路逻辑。

8. 发明授权

US6049224A Programmable logic device with logic cells having a flexible input structure 失效
标题翻译：具有逻辑单元的可编程逻辑器件具有灵活的输入结构
公开(公告)号：US6049224A
公开(公告)日：2000-04-11
申请号：US950624
申请日：1997-10-15
申请人： Barry K. Britton , Ian L. McEwen , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
发明人： Barry K. Britton , Ian L. McEwen , Ho T. Nguyen , Satwant Singh , Carolyn W. Spivak , Richard G. Stuby, Jr.
IPC分类号： H03K19/177 , H01L25/00 , H03K19/173
CPC分类号： H03K19/17728
摘要： A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.
摘要翻译：使用在路由资源和逻辑元件输入引脚之间具有可配置连接方案的逻辑单元来实现可编程逻辑器件，例如FPGA。例如，在一个实施例中，设备中的每个逻辑单元具有灵活的输入结构，其支持两个或多个不同的连接方案，其可以或可以不涉及输入共享，其中每个逻辑单元可以针对任何可用连接进行单独编程配置设备时的方案。因此，可以有效地对设备进行编程以实现用户的特定电路。本发明平衡了（1）通过限制路由资源和逻辑元件输入引脚之间的连接数来减少路由需求的竞争目标，以及（2）提供逻辑元件的最小约束编程。

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