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1. 发明授权

US06947309B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US06947309B2
公开(公告)日：2005-09-20
申请号：US10822807
申请日：2004-04-13
申请人： Kenya Watanabe , Mitsuhiro Yamamura
发明人： Kenya Watanabe , Mitsuhiro Yamamura
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device, in which wordlines and bitlines are hierarchized and influence of disturbance-noise is reduced, includes: first sub-wordline select switches, each of which are disposed between one of the main-wordlines and one end of one of the sub-wordlines provided for the one main-wordline; first sub-bitline select switches, each of which are disposed between one of the main-bitlines and one end of one of the sub-bitlines provided for the one main-bitline; second sub-wordline select switches, each of which are disposed between the other end of one of the sub-wordlines and the unselected wordline potential supply line; and second sub-bitline select switches, each of which are disposed between the other end of one of the sub-bitlines and the unselected bitline potential supply line, each of the first and second sub-wordline select switches and first and second sub-bitline select switches being driven independently at least in one of the sector regions.
摘要翻译：其中字线和位线被分级并且干扰噪声的影响减小的铁电存储器件包括：第一子字线选择开关，其中每一个被设置在一个主字线之间，一个子线之一为一条主要字线提供的文字; 第一子位线选择开关，每个开关分别位于主位线之一和为一个主位线提供的一个子位线的一端之间; 第二子字线选择开关，其中每一个设置在一个子字线的另一端和未选择的字线电位供应线之间; 以及第二子位线选择开关，其中每一个位于第一和第二子字线选择开关和第一和第二子位线之间，每个子位线选择开关设置在子位线之一的另一端和未选择的位线电位供应线之间至少在一个扇区中选择开关独立驱动。

2. 发明申请

US20050002216A1 Ferroelectric memory device 失效
公开(公告)号：US20050002216A1
公开(公告)日：2005-01-06
申请号：US10822807
申请日：2004-04-13
申请人： Kenya Watanabe , Mitsuhiro Yamamura
发明人： Kenya Watanabe , Mitsuhiro Yamamura
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device, in which wordlines and bitlines are hierarchized and influence of disturbance-noise is reduced, includes: first sub-wordline select switches, each of which are disposed between one of the main-wordlines and one end of one of the sub-wordlines provided for the one main-wordline; first sub-bitline select switches, each of which are disposed between one of the main-bitlines and one end of one of the sub-bitlines provided for the one main-bitline; second sub-wordline select switches, each of which are disposed between the other end of one of the sub-wordlines and the unselected wordline potential supply line; and second sub-bitline select switches, each of which are disposed between the other end of one of the sub-bitlines and the unselected bitline potential supply line, each of the first and second sub-wordline select switches and first and second sub-bitline select switches being driven independently at least in one of the sector regions.

3. 发明授权

US09035252B2 Detection circuit, sensor device, and electronic apparatus 有权
标题翻译：检测电路，传感器装置和电子设备
公开(公告)号：US09035252B2
公开(公告)日：2015-05-19
申请号：US13277695
申请日：2011-10-20
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G01J5/34 , G01J1/44 , H01L37/02 , G08B13/191
CPC分类号： G01J5/34 , G01J1/44 , G08B13/191 , H01L37/02
摘要： A detection circuit includes a pyroelectric element; a first P-type transistor provided between an output node and a low-potential-side power node of the detection circuit, a detection signal being inputted from the pyroelectric element to a gate of the first P-type transistor; and a second P-type transistor provided between a high-potential-side power node and the output node, a gate of the second P-type transistor being set to a reference voltage.
摘要翻译：检测电路包括热电元件; 设置在检测电路的输出节点和低电位侧功率节点之间的第一P型晶体管，从热电元件输入到第一P型晶体管的栅极的检测信号; 以及设置在高电位侧功率节点和输出节点之间的第二P型晶体管，第二P型晶体管的栅极被设定为参考电压。

4. 发明授权

US07460390B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US07460390B2
公开(公告)日：2008-12-02
申请号：US11616407
申请日：2006-12-27
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： When reading first memory cell data in a ferroelectric memory device, voltage on first bit lines changes. Therefore, controllers turn on first transistors in first read-out voltage generators based on the first bit line voltage, and control the first transistors' channel resistance. When the first transistors turn on, the pre-charged drain voltage lowers and the first read-out voltage generators output the lowered voltage as the first memory cell data's voltage. When reading second memory cell data, a second read-out voltage generator outputs a second transistor's drain voltage that is lowered based on the data as the second memory cell data's voltage. When the second read-out voltage generator outputs the read-out voltage, a reference voltage generator generates a reference voltage equal to the read-out voltage. Because the reference voltage generator has a higher voltage supply capacity than the second read-out voltage generator, the reference voltage is supplied to sense amplifiers.
摘要翻译：当在铁电存储器件中读取第一存储单元数据时，第一位线上的电压发生变化。因此，控制器基于第一位线电压来导通第一读出电压发生器中的第一晶体管，并且控制第一晶体管的沟道电阻。当第一晶体管导通时，预充电漏极电压降低，第一读出电压发生器输出降低的电压作为第一存储单元数据的电压。当读取第二存储单元数据时，第二读出电压发生器输出基于作为第二存储单元数据电压的数据降低的第二晶体管的漏极电压。当第二读出电压发生器输出读出电压时，参考电压发生器产生等于读出电压的参考电压。由于参考电压发生器具有比第二读出电压发生器更高的电源电压，所以参考电压被提供给读出放大器。

5. 发明授权

US06940742B2 Method of storing data in ferroelectric memory device 失效
标题翻译：在铁电存储器件中存储数据的方法
公开(公告)号：US06940742B2
公开(公告)日：2005-09-06
申请号：US10816854
申请日：2004-04-05
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G06F12/00 , G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A method of storing data in a ferroelectric memory device is capable of dealing with a program request during a read cycle or a change in program data during a program cycle. In this data storage method, the program cycle or the read cycle is performed for selected memory cells selected from among a plurality of memory cells, and each of the program cycle or the read cycle includes a period for writing data “0” and a period for writing data “1” into the selected memory cells. When a program request occurs in the period for writing the data “0” (read period) in the read cycle, the data “1” is written into the selected memory cells according to program data designated by the program request.
摘要翻译：在铁电存储器件中存储数据的方法能够在程序循环期间在读周期期间处理程序请求或改变程序数据。在该数据存储方法中，对从多个存储单元中选择的选择的存储单元执行编程周期或读周期，并且每个编程周期或读周期包括写数据“0”和周期用于将数据“1”写入所选存储单元。当在读周期中写入数据“0”（读周期）的周期中发生程序请求时，根据由程序请求指定的程序数据将数据“1”写入所选存储单元。

6. 发明申请

US20050122763A1 Ferroelectric memory device and electronic apparatus 失效
标题翻译：铁电存储器件和电子设备
公开(公告)号：US20050122763A1
公开(公告)日：2005-06-09
申请号：US10979084
申请日：2004-10-29
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G11C11/22 , G11C11/24 , G11C17/04
CPC分类号： G11C11/22
摘要： A ferroelectric memory device is provided comprising a first ferroelectric capacitor group having a plurality of ferroelectric capacitors coupled in series and in a ring shape, and a switching means which switches whether or not either ferroelectric capacitor of the first ferroelectric capacitor group is electrically coupled to a first bit line and a first plate line. It is preferable that the switching means comprises: a first switch provided between one end of a first ferroelectric capacitor out of the first ferroelectric capacitor group and a first bit line; a second switch provided between one end of a second ferroelectric capacitor adjoining the first ferroelectric capacitor and another end of the first ferroelectric capacitor, and a first plate line; and a third switch provided between the other end of the second ferroelectric capacitor and the first bit line.
摘要翻译：提供一种强电介质存储器件，包括具有多个串联耦合并呈环状的铁电电容器的第一铁电电容器组，以及切换装置，其切换第一铁电电容器组的铁电电容器是否电耦合到第一位线和第一板线。优选的是，开关装置包括：第一开关，设置在第一铁电电容器组之间的第一铁电电容器的一端和第一位线之间; 设置在与第一铁电电容器相邻的第二铁电电容器的一端和第一铁电电容器的另一端之间的第二开关和第一板线; 以及设置在第二铁电电容器的另一端和第一位线之间的第三开关。

7. 发明授权

US06842976B2 Method of connecting flat cable and terminal 有权
标题翻译：连接扁平电缆和端子的方法
公开(公告)号：US06842976B2
公开(公告)日：2005-01-18
申请号：US10219701
申请日：2002-08-14
申请人： Noritsugu Enomoto , Yoshiyuki Suzuki , Mitsuhiro Yamamura
发明人： Noritsugu Enomoto , Yoshiyuki Suzuki , Mitsuhiro Yamamura
IPC分类号： H01R4/24 , H01R12/10 , H01R43/058 , H02G1/14 , H02G15/08 , H05K3/00 , H05K3/32 , H01K4/24 , H01K4/26 , H01K11/20
CPC分类号： H01R12/68 , H01R12/616 , H01R12/67 , H01R43/058 , H05K3/326 , Y10T29/49151 , Y10T29/49153 , Y10T29/49174 , Y10T29/49181 , Y10T29/49208 , Y10T29/49218 , Y10T29/49835 , Y10T29/49922
摘要： A method of connecting a flat cable and a terminal, comprising a sticking step in which cramp pieces (13b-13d) are stuck through a flat cable (10) to be received in corresponding cavities (15b, 15c) that are provided to allow the cramp pieces to maintain their shapes, and a cramping step in which the cramp pieces that have been stuck through the flat cable are bent and thereby cramped to the flat cable.
摘要翻译：一种连接扁平电缆和端子的方法，包括一个粘贴步骤，其中夹持片（13b-13d）通过扁平电缆（10）卡住以被接收在相应的空腔（15b，15c）中，夹持件以保持它们的形状，以及夹持步骤，其中已经通过扁平电缆卡住的夹持件弯曲并且由此被夹在扁平电缆上。

8. 发明授权

US07948788B2 Method for driving ferroelectric memory device, ferroelectric memory device, and electronic equipment 有权
标题翻译：铁电存储器件，铁电存储器件和电子设备的驱动方法
公开(公告)号：US07948788B2
公开(公告)日：2011-05-24
申请号：US12486947
申请日：2009-06-18
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C7/1006 , G11C11/22
摘要： A method for driving a ferroelectric memory device having a plurality of memory cells that store data and a memory cell for flag is provided. The method includes, upon writing to the plurality of memory cells, the steps of: reading data from the plurality of memory cells and the memory cell for flag; judging as to whether the data readout from the memory cell for flag is specified data; overwriting write data to the plurality of memory cells, and writing reverse data of the specified data to the memory cell for flag, when the data readout from the memory cell for flag is the specified data; and rewriting the data readout from the plurality of memory cells to the plurality of memory cells, and writing the reverse data to the memory cell for flag, when the data readout from the memory cell for flag is the reverse data.
摘要翻译：提供一种用于驱动具有存储数据的多个存储单元和用于标志的存储单元的铁电存储器件的方法。该方法包括：在向多个存储器单元写入时，从多个存储单元和存储单元读取数据以进行标志; 判断来自用于标志的存储单元的数据读出是否是指定数据; 当从用于标志的存储单元读出的数据是指定的数据时，写入数据到多个存储器单元，并将指定数据的反向数据写入到用于标志的存储单元; 并且当从用于标志的存储单元读出的数据是反向数据时，将从多个存储器单元读出的数据重新写入多个存储器单元，并将反向数据写入用于标志的存储单元。

9. 发明授权

US07616471B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US07616471B2
公开(公告)日：2009-11-10
申请号：US11454173
申请日：2006-06-15
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/062 , G11C7/067 , G11C7/12
摘要： A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells. The sense amplifiers each include a first n-MOS transistor, a first voltage being supplied to a source of the first n-MOS transistor; a first precharge unit precharging a drain of the first n-MOS transistor to a second voltage, which is a positive voltage that is higher than the first voltage; a transistor control unit that lowers the drain voltage that has been precharged to the second voltage by controlling a resistance between the source and the drain of the first n-MOS transistor in accordance with a voltage on a corresponding bit line, when data stored in the memory cells is read out to that bit line; and a voltage control unit that lowers the voltage of the bit line in accordance with the lowering of the voltage of the drain.
摘要翻译：铁电存储器阵列包括多个位线; 多个存储单元，连接到位线并存储预定的数据; 以及与位线对应地提供的多个读出放大器，以及放大从存储器单元读出的数据。感测放大器各自包括第一n-MOS晶体管，第一电压被提供给第一n-MOS晶体管的源极; 第一预充电单元将第一n-MOS晶体管的漏极预充电到第二电压，第二电压是高于第一电压的正电压; 晶体管控制单元，通过根据相应位线上的电压控制第一n-MOS晶体管的源极和漏极之间的电阻，将已经预充电的漏极电压降低到第二电压，当存储在存储单元被读出到该位线; 以及电压控制单元，其根据漏极的电压的降低而降低位线的电压。

10. 发明申请

US20060018151A1 Ferroelectric memory device and its driving method 有权
标题翻译：铁电存储器及其驱动方法
公开(公告)号：US20060018151A1
公开(公告)日：2006-01-26
申请号：US11157519
申请日：2005-06-21
申请人： Mitsuhiro Yamamura
发明人： Mitsuhiro Yamamura
IPC分类号： G11C11/00
CPC分类号： G11C11/22
摘要： A ferroelectric memory device equipped with a plurality of memory cells and a control section that stores memory data indicated by a data signal when a write control signal changes from a first logical value to a second logical value, the ferroelectric memory device wherein, when the write control signal indicates the first logical value, the control section writes preliminary data in a first memory cell, and when the write control signal changes from the first logical value to the second logical value, the control section retains the preliminary data in the first memory cell, or writes the memory data in the first memory cell to store the memory data in the first memory cell.
摘要翻译：配备有多个存储单元的铁电存储器件和控制部分，当写入控制信号从第一逻辑值变为第二逻辑值时，存储由数据信号指示的存储器数据，所述强电介质存储器件，当写入所述控制信号指示所述第一逻辑值，所述控制部将初步数据写入第一存储单元，并且当所述写入控制信号从所述第一逻辑值变为所述第二逻辑值时，所述控制部将所述初步数据保存在所述第一存储单元或者将存储器数据写入第一存储器单元中以将存储器数据存储在第一存储器单元中。

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