会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Electrostatic protection circuit
    • 静电保护电路
    • US07570467B2
    • 2009-08-04
    • US11237149
    • 2005-09-27
    • Kentaro WatanabeHiroyuki Yoshinaga
    • Kentaro WatanabeHiroyuki Yoshinaga
    • H02H9/00
    • H01L27/0262
    • An electrostatic protection circuit being an integrated circuit on a semiconductor substrate and including a first power supply terminal having a predetermined potential VDD, a second power supply terminal having a lower potential VSS than the predetermined potential, and an input/output terminal for a signal, the electrostatic protection circuit including: a first and second diodes having the respective cathode electrodes thereof connected in series at a first common connection point between the first power supply terminal and input/output terminal; a third and fourth diodes having the respective anode electrodes thereof connected in series at a second common connection point between the second power supply terminal and input/output terminal; a first discharge element, connected between the first and second common connection points, for discharging excessive static electricity; and a second discharge element, connected between the first and second power supply terminals, for discharging excessive static electricity.
    • 一种静电保护电路,是半导体衬底上的集成电路,包括具有预定电位VDD的第一电源端子,具有比预定电位低的电位VSS的第二电源端子和用于信号的输入/输出端子, 所述静电保护电路包括:第一和第二二极管,其第一和第二二极管具有在第一电源端子和输入/输出端子之间的第一公共连接点串联连接的各个阴极电极; 第三和第四二极管,其各自的阳极电极在第二电源端子和输入/输出端子之间的第二公共连接点处串联连接; 第一放电元件,连接在第一和第二公共连接点之间,用于释放过多的静电; 以及第二放电元件,连接在第一和第二电源端子之间,用于释放过多的静电。
    • 4. 发明申请
    • MANAGEMENT SYSTEM AND PROGRAM PRODUCT
    • 管理系统和程序产品
    • US20140040447A1
    • 2014-02-06
    • US13817379
    • 2012-07-31
    • Kentaro Watanabe
    • Kentaro Watanabe
    • H04L12/24
    • H04L41/50H04L41/0893
    • A management system for managing one or more information processing apparatuses through a network includes a storage part that stores various tables and a controller that controls execution of a predetermined operation according to an execution request of the operation. The storage part stores the predetermined operation and one or more realization means of the operation in association with each other. The controller receives the execution request of the operation, specifies one or more realization means of the operation corresponding to the operation, and selects realization means of the operation that can be executed from the specified one or more realization means on the basis of management information including configuration information and operation information of the information processing apparatuses.
    • 用于通过网络管理一个或多个信息处理设备的管理系统包括存储各种表的存储部分和根据操作的执行请求来控制预定操作的执行的控制器。 存储部分将预定的操作和操作的一个或多个实现装置相互关联地存储。 控制器接收操作的执行请求,指定与操作相对应的操作的一个或多个实现装置,并且基于包括以下的管理信息,从指定的一个或多个实现装置中选择可执行的操作的实现手段: 信息处理装置的配置信息和操作信息。
    • 5. 发明申请
    • METHOD OF DATA MIGRATION AND INFORMATION STORAGE SYSTEM
    • 数据迁移和信息存储系统的方法
    • US20130311740A1
    • 2013-11-21
    • US13512616
    • 2012-05-17
    • Kentaro WatanabeTakashi TameshigeMasayasu AsanoMutsumi HosoyaHideo Saito
    • Kentaro WatanabeTakashi TameshigeMasayasu AsanoMutsumi HosoyaHideo Saito
    • G06F12/02
    • G06F3/061G06F3/0647G06F3/0685
    • An example of the invention is a method of data migration from a source volume including storage areas of a plurality of source storage tiers different in performance capability to a destination volume including storage areas of a plurality of destination storage tiers different in performance capability, data relocation being performed among the plurality of source storage tiers in accordance with accesses to the source volume during the data migration. The method includes: starting the data migration between volumes from the source volume to the destination volume; acquiring information on a data arrangement in the source volume determined based on an access history to the source volume during the data migration between volumes from the source volume to the destination volume; and determining a data arrangement in the destination volume during the data migration between volumes based on the data arrangement indicated by the acquired information.
    • 本发明的一个示例是从包括在性能能力不同的多个源存储层的存储区域的源卷的数据迁移到包括性能能力不同的多个目的地存储层的存储区域的目的地卷的数据迁移的方法,数据重定位 在数据迁移期间根据对源卷的访问在多个源存储层之间执行。 该方法包括:启动从源卷到目标卷的卷之间的数据迁移; 在从源卷到目的地卷的卷之间的数据迁移期间,基于对源卷的访问历史确定的源卷中的数据排列的信息; 以及基于由所获取的信息指示的数据排列,在卷之间的数据迁移期间确定目的地卷中的数据排列。
    • 8. 发明授权
    • Semiconductor device including overcurrent protection element
    • 半导体装置包括过电流保护元件
    • US07999324B2
    • 2011-08-16
    • US11291436
    • 2005-11-30
    • Naoyuki ShigyoKentaro Watanabe
    • Naoyuki ShigyoKentaro Watanabe
    • H01L23/62H01L29/76
    • H01L29/665H01L27/0266H01L29/0653H01L29/41758H01L29/4238H01L29/7833H01L29/7835H01L2924/0002H01L2924/00
    • A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region. The silicide layer is formed on each of the first, second, third semiconductor regions and the gate electrode.
    • 半导体器件包括第一,第二,第三和第四半导体区域,栅电极和硅化物层。 第一,第二和第三半导体区域形成在半导体衬底中,同时彼此间隔开。 第四半导体区域形成在第二半导体区域和第三半导体区域之间的半导体衬底中,并且具有高于第一,第二和第三半导体区域的电阻。 在垂直于连接第一和第二半导体区域的方向的方向上,第四半导体区域的宽度小于夹在第一半导体区域和第二半导体区域之间的半导体衬底的宽度。 栅极电极形成在第一半导体区域和第二半导体区域之间的半导体衬底之上。 硅化物层形成在第一,第二,第三半导体区域和栅电极中的每一个上。