专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100147574A1 WIRING BOARD AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线板及其制造方法
公开(公告)号：US20100147574A1
公开(公告)日：2010-06-17
申请号：US12632112
申请日：2009-12-07
申请人： Kentaro KANEKO , Hidemi Atobe
发明人： Kentaro KANEKO , Hidemi Atobe
IPC分类号： H01R12/06 , H01K3/10
CPC分类号： H01L25/105 , H01L21/4853 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L25/16 , H01L25/50 , H01L2221/68345 , H01L2224/13099 , H01L2224/1411 , H01L2224/16 , H01L2224/16237 , H01L2224/16238 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/19105 , H05K1/113 , H05K3/205 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09045 , H05K2201/09436 , H05K2201/09527 , Y10T29/49162
摘要： A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to each other through vias formed in the insulating layers. In the peripheral region around the chip mounting area of the outermost insulating layer on one of both surfaces of the board, a pad is formed in a bump shape to cover a surface of a portion of the outermost insulating layer, the portion being formed to protrude, and a pad whose surface is exposed from the insulating layer is arranged in the chip mounting area. A chip is flip-chip bonded to the pad of the package, and another package is bonded to the bump shaped pad in a peripheral region around the chip (package-on-package bonding).
摘要翻译：布线板（封装）具有多个布线层一层叠置的结构，绝缘层分别插入在相应的两个布线层之间，并且布线层通过形成在绝缘层中的通孔彼此连接。在板的两个表面之一的最外层绝缘层的芯片安装区域周围的周边区域中，形成凸起形状的焊盘以覆盖最外层绝缘层的一部分的表面，该部分形成为突出并且其表面从绝缘层露出的焊盘被布置在芯片安装区域中。将芯片倒装芯片贴合到封装的焊盘上，另一个封装在芯片周围的周边区域（封装在封装的封装上）结合到凸块形焊盘。

2. 发明申请

US20120155048A1 WIRING BOARD, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THEM 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：US20120155048A1
公开(公告)日：2012-06-21
申请号：US13404627
申请日：2012-02-24
申请人： Kentaro KANEKO
发明人： Kentaro KANEKO
IPC分类号： H05K7/06 , H05K1/02 , H01L21/50 , H05K3/00 , H01L21/58
CPC分类号： H01L21/6835 , H01L21/563 , H01L23/3121 , H01L23/3142 , H01L24/16 , H01L24/48 , H01L2221/68345 , H01L2224/16 , H01L2224/16225 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/83385 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/181 , H05K3/205 , H05K3/28 , H05K3/381 , H05K3/382 , H05K3/4682 , H05K2201/10674 , H05K2203/0152 , H05K2203/1152 , Y10T29/41 , Y10T29/49126 , Y10T29/4916 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.
摘要翻译：提供了在支撑体的表面上设置电介质层和布线层以形成中间体的步骤，从中间体移除支撑体以获得布线板，并在支撑体的表面上进行粗糙化处理在中间体形成步骤之前。

3. 发明申请

US20110147924A1 WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线基板及其制造方法
公开(公告)号：US20110147924A1
公开(公告)日：2011-06-23
申请号：US12967322
申请日：2010-12-14
申请人： Kentaro KANEKO , Kotaro KODANI
发明人： Kentaro KANEKO , Kotaro KODANI
IPC分类号： H01L23/52 , H01L21/441
CPC分类号： H01L23/49827 , H01L23/49816 , H01L23/49822 , H01L23/49866 , H01L2924/0002 , H01L2924/00
摘要： A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.
摘要翻译：布线基板包括绝缘层，埋在绝缘层中的布线层，以及连接焊盘，该连接焊盘经由设置在绝缘层中的通路导体连接到布线层，并且至少一部分埋设在绝缘层的外表面侧所述绝缘层，其中所述连接焊盘包括布置在所述外表面侧上的第一金属层（第一铜层），布置在所述第一金属层的内层侧的表面上的中间金属层（镍层）以及布置在中间金属层的内层侧的表面上的第二金属层（第二铜层），并且中间金属层的硬度高于第一金属层和第二金属层的硬度。

4. 发明申请

US20120175153A1 WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：接线基板及其制造方法
公开(公告)号：US20120175153A1
公开(公告)日：2012-07-12
申请号：US13344864
申请日：2012-01-06
申请人： Kentaro KANEKO , Toshiaki AOKI , Kazuhiro KOBAYASHI , Kotaro KODANI , Junichi NAKAMURA
发明人： Kentaro KANEKO , Toshiaki AOKI , Kazuhiro KOBAYASHI , Kotaro KODANI , Junichi NAKAMURA
IPC分类号： H05K1/02 , H05K3/42
CPC分类号： H05K1/113 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15174 , H05K3/4682 , H05K2203/0152 , H05K2203/016 , Y10T29/49165 , H01L2924/00
摘要： A wiring substrate includes plural insulating layers including an outermost insulating layer; and plural wiring layers which are alternately laminated between the insulating layers and include outermost wiring layers exposed from the outermost insulating layer and through wirings having electrode pads on end portions of the through wirings and penetrating through the outermost insulating layer, wherein the electrode pads of the through wirings are exposed from the outermost insulating layer, and a part of the outermost wiring layers overlaps the end portions of the through wirings and is connected to the through wirings.
摘要翻译：布线基板包括包括最外绝缘层的多个绝缘层; 以及多个布线层，交替层叠在绝缘层之间，并且包括从最外层绝缘层露出的最外面布线层，并且穿过在通孔布线的端部上穿过最外层绝缘层的电极焊盘的布线，其中，通过布线从最外侧绝缘层露出，并且最外面的布线层的一部分与贯通配线的端部重叠，并与贯通布线连接。

5. 发明申请

US20100147560A1 WIRING BOARD AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线板及其制造方法
公开(公告)号：US20100147560A1
公开(公告)日：2010-06-17
申请号：US12628281
申请日：2009-12-01
申请人： Kentaro KANEKO
发明人： Kentaro KANEKO
IPC分类号： H05K1/02 , B32B37/00
CPC分类号： H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/50 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/1058 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3511 , H05K1/183 , H05K3/205 , H05K3/4682 , H05K3/4697 , H05K2201/09472 , H05K2201/09481 , H05K2201/10674 , H05K2203/0369 , H05K2203/0376 , Y10T156/10 , H01L2924/00012 , H01L2924/00
摘要： A wiring board (package) includes: a cavity formed at a position corresponding to a chip mounting area of the outermost insulating layer on one side of both surfaces of the wiring board; a pad exposed from the surface of the insulating layer in the cavity; and a pad exposed from the surface of the insulating layer in a peripheral region of the cavity. A chip is flip-chip bonded to the pads in the cavity of the package, and another package is bonded to the pads in the peripheral region of the cavity, to thereby form a semiconductor device having a package on package (POP) structure.
摘要翻译：布线板（封装）包括：形成在与布线板的两面的一侧的最外层绝缘层的芯片安装区域对应的位置的空腔; 从空腔中的绝缘层的表面暴露的焊盘; 以及在空腔的周边区域中从绝缘层的表面暴露的焊盘。将芯片倒装芯片结合到封装空腔中的焊盘，另一个封装结合到空腔周边区域中的焊盘，从而形成具有封装封装（POP）结构的半导体器件。

6. 发明申请

US20100139962A1 WIRING BOARD AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：US20100139962A1
公开(公告)日：2010-06-10
申请号：US12628284
申请日：2009-12-01
申请人： Kentaro KANEKO
发明人： Kentaro KANEKO
IPC分类号： H05K1/16 , H05K3/00
CPC分类号： H05K3/0014 , H01L21/4857 , H01L21/563 , H01L23/49816 , H01L23/49822 , H01L24/32 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/26175 , H01L2224/27013 , H01L2224/32057 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83385 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/0271 , H05K1/112 , H05K3/305 , H05K3/4682 , H05K2201/09036 , H05K2201/09045 , H05K2201/09136 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： A wiring board includes a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer (resin layer) interposed therebetween, and the wiring layers are connected to each other through a via formed in each of the resin layers. A recessed portion is formed in an annular shape surrounding a chip mounting area on the outermost resin layer on a chip mounting surface side of the wiring board. Alternatively, a projected portion is formed instead of the recessed portion.
摘要翻译：布线基板包括其中多个布线层一层叠置在其上的绝缘层（树脂层）之间的结构，并且布线层通过形成在每个树脂层中的通孔相互连接。凹陷部形成为围绕布线基板的芯片安装面侧的最外层树脂层上的芯片安装区域的环状。或者，形成突出部分而不是凹部。

7. 发明申请

US20130075145A1 WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线基板及其制造方法
公开(公告)号：US20130075145A1
公开(公告)日：2013-03-28
申请号：US13616348
申请日：2012-09-14
申请人： Kentaro KANEKO , Toshimitsu Omiya , Kotaro Kodani , Junichi Nakamura , Kazuhiro Kobayashi
发明人： Kentaro KANEKO , Toshimitsu Omiya , Kotaro Kodani , Junichi Nakamura , Kazuhiro Kobayashi
IPC分类号： H05K1/11 , H05K3/10
CPC分类号： H05K3/188 , C25D5/022 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/49822 , H01L23/544 , H01L24/16 , H01L24/81 , H01L2221/68345 , H01L2221/68381 , H01L2223/54426 , H01L2223/54486 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/92125 , H01L2924/12042 , H01L2924/15311 , H05K1/113 , H05K3/0017 , H05K3/46 , H05K3/4682 , H05K2201/0376 , H05K2201/09036 , H05K2203/0369 , H05K2203/0376 , H05K2203/06 , Y10T29/49155 , H01L2924/00
摘要： A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.
摘要翻译：布线基板包括绝缘层，埋置在绝缘层中的连接焊盘，该连接焊盘处于连接焊盘的上表面从绝缘层的上表面露出的状态以及下表面和侧表面的至少一部分所述连接焊盘与所述绝缘层接触，以及形成在所述绝缘层中的所述连接焊盘的外周部分的凹陷高度差部分，其中所述连接焊盘的上表面和所述绝缘层的上表面被布置在相同的高度

8. 发明申请

US20100032196A1 MULTILAYER WIRING BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：多层接线板，半导体封装及其制造方法
公开(公告)号：US20100032196A1
公开(公告)日：2010-02-11
申请号：US12537391
申请日：2009-08-07
申请人： Kentaro KANEKO , Kazuhiro Kobayashi , Yoshiki Okushima , Kotaro Kodani
发明人： Kentaro KANEKO , Kazuhiro Kobayashi , Yoshiki Okushima , Kotaro Kodani
IPC分类号： H05K1/16 , H05K1/11 , B32B37/00
CPC分类号： H05K1/113 , B32B37/02 , B32B2457/08 , H01L21/4846 , H01L21/563 , H01L21/6835 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/02 , H01L24/16 , H01L2221/68345 , H01L2224/0401 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/20 , H05K3/421 , H05K3/4644 , H05K3/4682 , H05K2201/037 , H05K2201/09527 , H05K2201/0979 , H05K2201/09981 , Y10T156/10 , H01L2924/00012 , H01L2924/00
摘要： In a multilayer wiring board having a wiring layer, a pad, an insulating layer provided between the wiring layer and the pad, and a plurality of connecting vias provided on the insulating layer and connecting the wiring layer to the pad, the connecting vias are provided on a peripheral edge of the pad.
摘要翻译：在具有布线层，焊盘，设置在布线层和焊盘之间的绝缘层以及设置在绝缘层上并将布线层连接到焊盘的多个连接通孔的多层布线板中，提供连接通孔在垫的外围边缘。

9. 发明申请

US20090095514A1 WIRING BOARD, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THEM 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：US20090095514A1
公开(公告)日：2009-04-16
申请号：US12244232
申请日：2008-10-02
申请人： Kentaro KANEKO
发明人： Kentaro KANEKO
IPC分类号： H05K1/00 , H05K3/36 , H05K1/11 , H05K1/16
CPC分类号： H01L21/6835 , H01L21/563 , H01L23/3121 , H01L23/3142 , H01L24/16 , H01L24/48 , H01L2221/68345 , H01L2224/16 , H01L2224/16225 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/83385 , H01L2924/00014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15174 , H01L2924/181 , H05K3/205 , H05K3/28 , H05K3/381 , H05K3/382 , H05K3/4682 , H05K2201/10674 , H05K2203/0152 , H05K2203/1152 , Y10T29/41 , Y10T29/49126 , Y10T29/4916 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.
摘要翻译：提供了在支撑体的表面上设置电介质层和布线层以形成中间体的步骤，从中间体移除支撑体以获得布线板，并在支撑体的表面上进行粗糙化处理在中间体形成步骤之前。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式