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1. 发明授权

US08674455B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08674455B2
公开(公告)日：2014-03-18
申请号：US13334964
申请日：2011-12-22
申请人： Kensuke Okonogi , Kazuhiro Nojima , Kiyonori Oyu
发明人： Kensuke Okonogi , Kazuhiro Nojima , Kiyonori Oyu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/823892 , H01L27/0928 , H01L27/10873
摘要： A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 μm depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
摘要翻译：提供一种半导体器件，其包括从P型半导体衬底的表面开始的深度为0.2至1μm的峰值浓度为2E + 17原子/ cm 3或更大的N阱，以及设置在P型半导体衬底的下方的区域 N阱，该区域含有比电子浓度高的P型杂质。

2. 发明授权

US07846826B2 Method of manufacturing a semiconductor device with multilayer sidewall 有权
标题翻译：制造具有多层侧壁的半导体器件的方法
公开(公告)号：US07846826B2
公开(公告)日：2010-12-07
申请号：US12246908
申请日：2008-10-07
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28114 , H01L21/28044 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
摘要翻译：栅极电介质膜，多晶硅膜，耐火金属如钨的膜和栅极盖电介质膜依次层压在半导体衬底上。通过蚀刻选择性地去除栅极电介质膜和难熔金属膜。此后，在栅极盖电介质膜，难熔金属膜和多晶硅膜的侧表面上形成包括氮化硅膜和氧化硅膜的双重保护膜。使用双重保护膜作为掩模蚀刻多晶硅膜。此后，半导体衬底被光氧化以在多晶硅膜的侧表面上形成氧化硅膜。因此，可以进一步减少具有多金属结构的栅电极，特别是DRAM的存储单元晶体管的MOSFET的结漏电。

3. 发明授权

US07632696B2 Semiconductor chip with a porous single crystal layer and manufacturing method of the same 有权
标题翻译：具有多孔单晶层的半导体芯片及其制造方法相同
公开(公告)号：US07632696B2
公开(公告)日：2009-12-15
申请号：US11372351
申请日：2006-03-10
申请人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
发明人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
IPC分类号： H01L21/00
CPC分类号： H01L21/306 , H01L21/304 , H01L21/78
摘要： A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.
摘要翻译：一种半导体芯片，包括设置有半导体器件区域的半导体衬底和多孔单晶层，其中半导体器件区域形成在半导体衬底的主表面部分上，并且多孔单晶层形成在半导体衬底的背面，并且包括从半导体衬底的背面在半导体衬底的内侧方向上连续延伸的腐蚀孔，形成在侵蚀孔的内表面上的氧化物膜和单晶部分。

4. 发明授权

US07666761B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07666761B2
公开(公告)日：2010-02-23
申请号：US11680814
申请日：2007-03-01
申请人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
发明人： Kiyonori Oyu , Kensuke Okonogi , Hirotaka Kobayashi , Koji Hamada
IPC分类号： H01L21/322
CPC分类号： H01L21/3221 , H01L21/304
摘要： In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.
摘要翻译：在制造半导体器件时，第一吸气层形成在晶片的背面，然后第二吸气层形成在芯片的背面和侧表面上，允许这些吸气层用作捕获位置以抵抗金属污染，在组装过程中后侧研磨后产生。

5. 发明授权

US07129141B2 Method for manufacturing a semiconductor device having a low junction leakage current 有权
标题翻译：具有低结漏电流的半导体器件的制造方法
公开(公告)号：US07129141B2
公开(公告)日：2006-10-31
申请号：US11024623
申请日：2004-12-30
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L27/10855 , H01L27/10873
摘要： A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.
摘要翻译：一种用于制造DRAM器件的方法包括以特定剂量注入磷光体的步骤，并且对植入的荧光体进行热处理以进行扩散以形成源极/漏极区域，并将氟注入源极/漏极区域并对植入的氟进行热处理以进行扩散其中。由于在源极/漏极区域和沟道区域之间的冶金连接处形成的空位型缺陷引起的较低的结漏电流，所得到的DRAM存储单元具有较大的数据存储能力。

6. 发明申请

US20070092993A1 Semiconductor device packaging for avoiding metal contamination 审中-公开
标题翻译：用于避免金属污染的半导体器件封装
公开(公告)号：US20070092993A1
公开(公告)日：2007-04-26
申请号：US11583157
申请日：2006-10-19
申请人： Kiyonori Oyu , Kensuke Okonogi
发明人： Kiyonori Oyu , Kensuke Okonogi
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , H01L21/6835 , H01L24/32 , H01L24/50 , H01L24/83 , H01L24/86 , H01L2224/32225 , H01L2224/8385 , H01L2224/92148 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/12036 , H01L2924/15311 , H01L2924/3025 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor device manufacture method includes: bonding a main device surface of a semiconductor chip onto a package tape with adhesive material; and subjecting the semiconductor chip and the package tape to baking to cure the adhesive material. The baking of the semiconductor chip and the package tape is accompanied by supplying blow gas to a rear surface of the semiconductor chip.
摘要翻译：一种半导体器件制造方法，包括：用粘合剂材料将半导体芯片的主器件表面接合到封装带上; 并对半导体芯片和封装带进行烘烤以使粘合剂材料固化。半导体芯片和封装带的烘烤伴随着向半导体芯片的后表面供给吹气。

7. 发明申请

US20060249075A1 Semiconductor chip with a porous single crystal layer and manufacturing method of the same 有权
公开(公告)号：US20060249075A1
公开(公告)日：2006-11-09
申请号：US11372351
申请日：2006-03-10
申请人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
发明人： Kiyonori Oyu , Koji Hamada , Kensuke Okonogi , Hideharu Miyake , Yasushi Kozuki , Masaharu Watanabe
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/306 , H01L21/304 , H01L21/78
摘要： A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.

8. 发明申请

US20050164438A1 Method for manufacturing a semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20050164438A1
公开(公告)日：2005-07-28
申请号：US11043085
申请日：2005-01-27
申请人： Kensuke Okonogi , Kiyonori Oyu
发明人： Kensuke Okonogi , Kiyonori Oyu
IPC分类号： H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8244 , H01L27/092 , H01L27/108 , H01L27/11 , H01L29/78 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/2652 , H01L21/2253 , H01L21/2658 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/10811 , H01L27/10873 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source/drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting the dopant at a dosage lower than 1×1013/cm2. The total dosage of the multi-step implantation ranges between 1×1013/cm2 and 3×1013/cm2.
摘要翻译：一种用于制造半导体器件中的MOS晶体管的方法包括通过使用多步骤注入和相关联的多步骤热处理在沟道层或源极/漏极区域中注入掺杂剂的步骤，其中所述多步骤注入包括每个用于以低于1×10 13 / cm 2的剂量注入掺杂剂的植入步骤。多步骤注入的总剂量范围为1×10 3 / cm 2和3×10 3 / cm 2 / 。

9. 发明申请

US20050153526A1 Method for manufacturing a semiconductor device having a low junction leakage current 失效
标题翻译：具有低结漏电流的半导体器件的制造方法
公开(公告)号：US20050153526A1
公开(公告)日：2005-07-14
申请号：US11029343
申请日：2005-01-06
申请人： Kiyonori Oyu , Kensuke Okonogi , Koji Hamada
发明人： Kiyonori Oyu , Kensuke Okonogi , Koji Hamada
IPC分类号： H01L21/8234 , H01L21/30 , H01L21/324 , H01L21/336 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78 , H01L21/322 , H01L21/425 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/3003 , H01L21/324 , H01L27/10814 , H01L27/10873 , H01L29/6659
摘要： A method for manufacturing a DRAM device includes a hydrogenating step conducted to source/drain diffused regions in a hydrogen ambient at a substrate temperature not lower than 350 degrees C., and a dehydrogenating step in an inactive gas ambient at a substrate temperature of lower than 350 degrees C., before a packaging step. If a defective cell having a lower refreshing time is found in the test before the packaging step, the defective cell is replaced by a redundant cell. The resultant DRAM has a lower degradation in the refreshing characteristic after the packaging step.
摘要翻译：一种用于制造DRAM器件的方法包括：在不低于350℃的衬底温度下，在氢环境中对源极/漏极扩散区域进行加氢步骤，以及在低于350℃的衬底温度下的非活性气体环境中的脱氢步骤 350摄氏度，包装步骤之前。如果在包装步骤之前的测试中发现具有较低刷新时间的缺陷单元，则由冗余单元替换缺陷单元。所得的DRAM在包装步骤之后的刷新特性中具有较低的劣化。

10. 发明授权

US07338876B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07338876B2
公开(公告)日：2008-03-04
申请号：US11039857
申请日：2005-01-24
申请人： Kensuke Okonogi , Kiyonori Oyu
发明人： Kensuke Okonogi , Kiyonori Oyu
IPC分类号： H01L21/331
CPC分类号： H01L27/10873 , H01L21/2652 , H01L21/324 , H01L27/10814 , H01L29/6659
摘要： A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.
摘要翻译：一种用于形成半导体存储器件的方法包括以下步骤：在半导体衬底中注入掺杂剂; 在氧化环境中热处理半导体衬底以扩散掺杂剂以在半导体衬底中形成扩散区域; 以及形成各自包括具有扩散区域的MOS晶体管作为源/漏区的存储单元。

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