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1. 发明授权

US06492669B2 Semiconductor device with schottky electrode having high schottky barrier 有权
标题翻译：肖特基电极具有高肖特基势垒的半导体器件
公开(公告)号：US06492669B2
公开(公告)日：2002-12-10
申请号：US09892567
申请日：2001-06-28
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L2980
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/2003 , H01L29/475 , H01L29/7783
摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.
摘要翻译：在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。载体供应层由AlGaN组成并具有拉伸应变。肖特基层由InGaN组成并具有压应变。在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

2. 发明授权

US06465814B2 Semiconductor device 有权
公开(公告)号：US06465814B2
公开(公告)日：2002-10-15
申请号：US09891419
申请日：2001-06-27
申请人： Kensuke Kasahara , Yasuo Ohno , Masaaki Kuzuhara , Hironobu Miyamoto , Yuji Ando , Tatsuo Nakayama , Kazuaki Kunihiro , Nobuyuki Hayama , Yuji Takahashi , Kouji Matsunaga
发明人： Kensuke Kasahara , Yasuo Ohno , Masaaki Kuzuhara , Hironobu Miyamoto , Yuji Ando , Tatsuo Nakayama , Kazuaki Kunihiro , Nobuyuki Hayama , Yuji Takahashi , Kouji Matsunaga
IPC分类号： H01L31072
CPC分类号： H01L29/7786 , H01L21/28575 , H01L29/2003 , H01L29/42316
摘要： A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

3. 发明授权

US06440822B1 Method of manufacturing semiconductor device with sidewall metal layers 失效
标题翻译：制造具有侧壁金属层的半导体器件的方法
公开(公告)号：US06440822B1
公开(公告)日：2002-08-27
申请号：US09901424
申请日：2001-07-09
申请人： Nobuyuki Hayama , Masaaki Kuzuhara , Kouji Matsunaga , Tatsuo Nakayama , Yuji Takahashi , Yasuo Ohno , Kazuaki Kunihiro , Kensuke Kasahara , Hironobu Miyamoto , Yuji Ando
发明人： Nobuyuki Hayama , Masaaki Kuzuhara , Kouji Matsunaga , Tatsuo Nakayama , Yuji Takahashi , Yasuo Ohno , Kazuaki Kunihiro , Kensuke Kasahara , Hironobu Miyamoto , Yuji Ando
IPC分类号： H01L21301
CPC分类号： H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/3677 , H01L2221/68327 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.
摘要翻译：在制造半导体器件的方法中，沟槽部分形成在衬底的相对表面部分之一的一侧上。每个沟槽部分的一部分由形成在基板的一个表面部分上的电源金属层覆盖。衬底被固定到支撑件，使得衬底的一个表面适合于支撑件。使用沟槽部分将芯片与衬底分离。在芯片的侧表面部分和芯片的另一个表面部分上形成导电膜。然后，芯片与支架分离。

4. 发明授权

US06552373B2 Hetero-junction field effect transistor having an intermediate layer 有权
标题翻译：具有中间层的异质结场效应晶体管
公开(公告)号：US06552373B2
公开(公告)日：2003-04-22
申请号：US09818587
申请日：2001-03-28
申请人： Yuji Ando , Hironobu Miyamoto , Naotaka Iwata , Koji Matsunaga , Masaaki Kuzuhara , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi , Tatsuo Nakayama , Nobuyuki Hayama , Yasuo Ohno
发明人： Yuji Ando , Hironobu Miyamoto , Naotaka Iwata , Koji Matsunaga , Masaaki Kuzuhara , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi , Tatsuo Nakayama , Nobuyuki Hayama , Yasuo Ohno
IPC分类号： H01L31072
CPC分类号： H01L29/7787 , H01L29/2003
摘要： A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.
摘要翻译：异质结FET在电子供给层和n型盖层之间具有包括n型杂质掺杂层的中间层。中间层通过离子化的正电荷抵消在电子供给层和n型覆盖层之间产生的极化的负电荷，从而减少对电子的阻挡和源极/漏极电阻。

5. 发明授权

US06476431B1 Field effect transistor with barrier layer to prevent avalanche breakdown current from reaching gate and method for manufacturing the same 失效
标题翻译：具有阻挡层的场效应晶体管，以防止到达栅极的雪崩击穿电流及其制造方法
公开(公告)号：US06476431B1
公开(公告)日：2002-11-05
申请号：US09438840
申请日：1999-11-12
申请人： Yasuo Ohno , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi
发明人： Yasuo Ohno , Kensuke Kasahara , Kazuaki Kunihiro , Yuji Takahashi
IPC分类号： H01L2980
CPC分类号： H01L29/812 , H01L29/1075
摘要： A p-type layer and an n-type layer which constitute a barrier layer are provided, and a leak of the holes at the time of the negative bias accompanying the p-type layer buffer required for the higher tolerance voltage is suppressed, and the discharge of the holes at the positive bias can be efficiently carried out. The tolerance voltage at the time of the OFF state is raised at the p-type layer buffer, and the tolerance voltage at the time of the ON state at the discharge of the holes is raised. Since no leak is generated from the p-type layer, the drain current is not lowered, and a higher output can be realized both in terms of the current and in terms of the voltage.
摘要翻译：设置构成阻挡层的p型层和n型层，抑制伴随着较高公差电压所需的p型层缓冲器的负偏压时的空穴泄漏，可以有效地进行正偏压下的孔的放电。在p型层缓冲器处，断开状态时的公差电压升高，并且在孔的放电时的接通状态时的容许电压升高。由于不会从p型层产生泄漏，所以漏极电流不降低，并且在电流和电压方面都可以实现更高的输出。

6. 发明授权

US06373082B1 Compound semiconductor field effect transistor 失效
标题翻译：复合半导体场效应晶体管
公开(公告)号：US06373082B1
公开(公告)日：2002-04-16
申请号：US09205707
申请日：1998-12-04
申请人： Yasuo Ohno , Yuji Takahashi , Kazuaki Kunihiro
发明人： Yasuo Ohno , Yuji Takahashi , Kazuaki Kunihiro
IPC分类号： H01L31119
CPC分类号： H01L23/4824 , H01L21/761 , H01L24/06 , H01L29/1029 , H01L29/42316 , H01L29/812 , H01L2224/48091 , H01L2924/12036 , H01L2924/1306 , H01L2924/13063 , H01L2924/13064 , H01L2924/00014 , H01L2924/00
摘要： A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.
摘要翻译：一种化合物半导体场效应晶体管，其在栅电极和漏电极之间具有非栅极区，其为不被栅电极覆盖的沟道区，其中在非栅极区中形成多个隔离区它们在沟道电流的方向上延伸并与栅电极接触的方式。该化合物半导体场效应晶体管在漏极和栅极之间的击穿电压得到改善，并且保持了晶体管的高速可操作性。

7. 发明授权

US06278144B1 Field-effect transistor and method for manufacturing the field effect transistor 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US06278144B1
公开(公告)日：2001-08-21
申请号：US09248490
申请日：1999-02-10
申请人： Kazuaki Kunihiro , Yasuo Ohno , Yuji Takahashi
发明人： Kazuaki Kunihiro , Yasuo Ohno , Yuji Takahashi
IPC分类号： H01L2980
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/66462 , H01L29/7783 , H01L29/8128
摘要： A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N2 and thickness D of the second conductivity layer are such that the following relationship holds: d > 2 ⁢ ϵ S ⁢ φ S eN 2 + 2 ⁢ ϵ S ⁢ V bi eN 2 ⁢ N 1 N 1 + N 2 wherein N1, is the impurity concentration of the first conductivity epitaxial layer, &phgr;s, &egr;s and Vbi, are surface potential, dielectric constant and a diffused potential, respectively, of the second conductivity epitaxial layer, and e is an elementary charge of electron. An electrically neutral region is formed in the second conductivity epitaxial layer when no voltage is applied between the gate and the source region, whereby the electrically neutral region functions similarly to the gate of a cascode-connected MOSFET, which improves the breakdown voltage of the FET.
摘要翻译：高功率FET具有覆盖半绝缘衬底的第一导电外延层，第二导电外延层，与第二导电层肖特基接触的栅极，以及与第二导电层欧姆接触的源极和漏极区。第二导电层的杂质浓度N2和厚度D使得以下关系成立：其中N1是第一导电外延层的杂质浓度，phis，εis和Vbi，是表面电位，介电常数和扩散电位，分别是第二导电外延层，e是电子的基本电荷。当在栅极和源极区之间没有施加电压时，在第二导电外延层中形成电中性区域，由此电中性区域类似于共源共栅MOSFET的栅极起作用，这改善了FET的击穿电压。

8. 发明授权

US5949096A Field effect transistor with stabilized threshold voltage 有权
标题翻译：具有稳定阈值电压的场效应晶体管
公开(公告)号：US5949096A
公开(公告)日：1999-09-07
申请号：US150775
申请日：1998-09-10
申请人： Satoru Ohkubo , Yasuo Ohno , Kazuaki Kunihiro
发明人： Satoru Ohkubo , Yasuo Ohno , Kazuaki Kunihiro
IPC分类号： H01L29/872 , H01L21/338 , H01L29/47 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L29/80
CPC分类号： H01L29/7787
摘要： In a field effect transistor, a semiconductor channel layer is formed for carriers to run therein, and a first conductive semiconductor carrier supply layer is formed on the channel layer. Also, a second conductive semiconductor layer has a conductive type opposite to the carrier supply layer or contacts the gate electrode and is formed of same materials as the carrier supply layer. A third conductive semiconductor layer is formed on the layer having a conductive type opposite to the carrier supply layer or contacting the gate electrode and has the same conductive type of the carrier supply layer. A schottky gate electrode is formed in contact with the second conductive semiconductor layer.
摘要翻译：在场效应晶体管中，形成用于载流子的半导体沟道层，在沟道层上形成第一导电性半导体载体供给层。此外，第二导电半导体层具有与载体供给层相反的导电类型或与栅电极接触，并且由与载体供给层相同的材料形成。第三导电半导体层形成在具有与载体供给层相反的导电类型或与栅电极接触的层上，并且具有与载体供给层相同的导电类型。形成与第二导电半导体层接触的肖特基栅电极。

9. 发明授权

US08072261B2 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US08072261B2
公开(公告)日：2011-12-06
申请号：US12520276
申请日：2007-12-13
申请人： Shingo Yamanouchi , Kazuaki Kunihiro
发明人： Shingo Yamanouchi , Kazuaki Kunihiro
IPC分类号： H03F1/02
CPC分类号： H03F1/0227 , H03F1/02 , H03F1/0222 , H03F1/3205 , H03F3/24 , H03F3/245 , H03F2200/324 , H03F2200/451 , H04B2001/045
摘要： A power amplifier based on EER technology or ET technology extracts an amplitude-modulated component from a modulated signal as an input signal which includes the amplitude-modulated component and a phase-modulated component, and decomposes the amplitude-modulated component into two control signals whose product is proportional to the amplitude-modulated component. One of the control signals is amplified by a highly efficient amplifier, and thereafter is used to amplitude-modulate an output from an RF amplifier. The other control signal is converted by a pulse modulator into a rectangular-wave signal, which is then mixed with the phase-modulated component or the modulated signal and input to the RF amplifier.
摘要翻译：基于EER技术或ET技术的功率放大器从调制信号中提取幅度调制分量作为包括幅度调制分量和相位调制分量的输入信号，并将幅度调制分量分解为两个控制信号，产品与调幅分量成正比。其中一个控制信号被高效放大器放大，此后用于对RF放大器的输出进行幅度调制。另一个控制信号由脉冲调制器转换成矩形波信号，然后与相位调制分量或调制信号混合并输入到RF放大器。

10. 发明申请

US20110279180A1 POWER AMPLIFIER AND POWER AMPLIFYING METHOD 有权
标题翻译：功率放大器和功率放大方法
公开(公告)号：US20110279180A1
公开(公告)日：2011-11-17
申请号：US13143417
申请日：2010-01-27
申请人： Shingo Yamanouchi , Kazuaki Kunihiro , Kazumi Shiikuma
发明人： Shingo Yamanouchi , Kazuaki Kunihiro , Kazumi Shiikuma
IPC分类号： H03F1/00
CPC分类号： H03F1/0227 , H03F1/32 , H03F3/189 , H03F3/211 , H03F3/245 , H03F2200/204 , H03F2200/411 , H03F2200/432 , H03F2200/451 , H03F2203/21142
摘要： An aspect of a power amplifier according to the present invention is a power amplifier that amplifies a modulated signal including amplitude modulated components and phase modulated components, the power amplifier including a first voltage source 21 that amplifies low-frequency components of the amplitude modulated components of the modulated signal to output a first voltage VC_L, a second voltage source 22 that amplifies high-frequency components of the amplitude modulated components of the modulated signal to output a second voltage VC_H, a current source 24 that amplifies amplitude components of the modulated signal to output a current, a combiner circuit 23 that combines the first voltage VC_L, the second voltage VC_H, and a current IM to generate a modulated power supply signal VOUT, and an RF amplifier 30 that amplifies a signal obtained by up-converting the modulated signal to a carrier frequency and outputs the amplified signal after modulating amplitude of the amplified signal by the modulated power supply signal VOUT. In this way, power efficiency of a circuit that generates a modulated power supply can be improved.
摘要翻译：根据本发明的功率放大器的一个方面是放大包括幅度调制分量和相位调制分量的调制信号的功率放大器，功率放大器包括：第一电压源21，其放大幅度调制分量的低频分量用于输出第一电压VC_L的调制信号，放大调制信号的幅度调制分量的高频分量以输出第二电压VC_H的第二电压源22，将调制信号的幅度分量放大到的电流源24 输出电流，组合第一电压VC_L，第二电压VC_H和电流IM的组合器电路23以产生调制电源信号VOUT，以及RF放大器30，其放大通过对调制信号进行上变频而获得的信号到载波频率，并且在调制放大信号的幅度之后输出放大的信号通过调制电源信号VOUT。以这种方式，可以提高产生调制电源的电路的功率效率。

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