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1. 发明授权

US07672268B2 Systems and methods for implementing double wide channels in a communication system 有权
标题翻译：在通信系统中实现双宽通道的系统和方法
公开(公告)号：US07672268B2
公开(公告)日：2010-03-02
申请号：US11156045
申请日：2005-06-17
申请人： Kenneth Stanwood , Timothy Leo Gallagher , Sheldon L. Gilbert , Yair Bourlas , Charles Bergan , Sam A. Liu , Darren Smith
发明人： Kenneth Stanwood , Timothy Leo Gallagher , Sheldon L. Gilbert , Yair Bourlas , Charles Bergan , Sam A. Liu , Darren Smith
IPC分类号： H04J3/16 , H04W72/00
CPC分类号： H04W28/20
摘要： In a system utilizing double wide communication channels, if a particular CPE requires a sustained rate that is greater than the bandwidth of a single channel, data to and from the CPE may be split across Channels A and B. Also, when the bandwidth requirements of a particular CPE peaks at a data rate greater than the capacity of a single channel, the CPE's data may be split across the two channels. In one embodiment, a single-wide CPE may communicate with the base station without knowing that it is communicating with a base station configured to communicate using a double wide channel.
摘要翻译：在使用双宽通信信道的系统中，如果特定的CPE需要比单个信道的带宽更长的持续速率，那么到CPE之间的数据可能会跨越信道A和B分裂。另外，当带宽要求特定的CPE以大于单个信道的容量的数据速率峰值，CPE的数据可以跨越两个信道被分离。在一个实施例中，单宽CPE可以与基站通信，而不知道它正在与被配置为使用双宽信道通信的基站通信。

2. 发明授权

US06944188B2 Synchronizing clocks across a communication link 失效
标题翻译：通过通信链路同步时钟
公开(公告)号：US06944188B2
公开(公告)日：2005-09-13
申请号：US09790443
申请日：2001-02-21
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
IPC分类号： H04J3/06 , H04L7/04 , H04L7/08 , H04L12/56 , G06F15/16 , H04B1/38 , H04L12/28 , H04Q7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率来定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

3. 发明申请

US20110122981A1 SYNCHRONIZING CLOCKS ACROSS A COMMUNICATION LINK 有权
标题翻译：通信链路同步时钟
公开(公告)号：US20110122981A1
公开(公告)日：2011-05-26
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

4. 发明授权

US07907640B2 Synchronizing clocks across a communication link 有权
标题翻译：通过通信链路同步时钟
公开(公告)号：US07907640B2
公开(公告)日：2011-03-15
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/16 , H04J3/06 , H04L7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
摘要翻译：从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。

5. 发明申请

US20090279652A1 Synchronizing Clocks Across a Communication Link 有权
标题翻译：通过通信链路同步时钟
公开(公告)号：US20090279652A1
公开(公告)日：2009-11-12
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

6. 发明授权

US08199779B2 Synchronizing clocks across a communication link 有权
标题翻译：通过通信链路同步时钟
公开(公告)号：US08199779B2
公开(公告)日：2012-06-12
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/16 , G06F15/16 , H04B1/38
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：用于在通信链路上同步一个或多个时钟的装置，系统和方法。从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。同步信号可以是以从机侧预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

7. 发明授权

US07583705B2 Synchronizing clocks across a communication link 失效
标题翻译：通过通信链路同步时钟
公开(公告)号：US07583705B2
公开(公告)日：2009-09-01
申请号：US11170391
申请日：2005-06-29
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04J3/06 , H04B1/38 , H04W4/00
CPC分类号： H04J3/0658 , H04L7/042 , H04L7/08 , H04W48/08 , H04W56/00 , H04W84/20
摘要： One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译：使用从主机发送到从时钟的同步信号，通过通信链路同步一个或多个时钟。同步信号可以是以从站所预期的间隔发送的预期信号模式。从时钟可以将接收的信号与预期同步信号的表示相关，以产生第一采样率的相关采样序列。将同步信号接收时间与预期时间进行比较，并调整从时钟直到时间匹配。通过通信链路同步的主和从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较。辅助独立时钟可以通过调整一个来独立同步，以使其与本地非常见时钟具有相同的差异，因为链路另一侧的辅助时钟与其本地非常见时钟相同。

8. 发明授权

US08928507B2 Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation 有权
标题翻译：时间交错模数转换器定时失配估计和补偿的方法和系统
公开(公告)号：US08928507B2
公开(公告)日：2015-01-06
申请号：US13936385
申请日：2013-07-08
申请人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
IPC分类号： H03M1/06 , H03M1/50
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may include a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
摘要翻译：用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，使用时间交织的模数转换器（ADC）将模拟信号转换成数字信号，以及通过使用在期望频率带宽内的频率上的去相关算法来估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。解相关算法可以包括对称自适应去相关算法。所接收的模拟信号可以由芯片上的校准音发生器产生。混叠信号可以与来自乘法器的输出信号相加。复数耦合系数可以利用求和信号上的去相关算法来确定。乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

9. 发明申请

US20140009318A1 METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION 有权
标题翻译：时间间隔模拟数字转换器时序误差估计与补偿的方法与系统
公开(公告)号：US20140009318A1
公开(公告)日：2014-01-09
申请号：US13936385
申请日：2013-07-08
申请人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
发明人： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
IPC分类号： H03M1/50
CPC分类号： H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
摘要翻译：用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号，以及通过使用在期望频率带宽内的频率上的去相关算法来估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。解相关算法可以包括对称自适应去相关算法。所接收的模拟信号可以由芯片上的校准音发生器产生。混叠信号可以与来自乘法器的输出信号相加。复数耦合系数可以利用求和信号上的去相关算法来确定。乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。

10. 发明授权

US07589627B2 Creation of environments to detect wireless devices 失效
标题翻译：创建检测无线设备的环境
公开(公告)号：US07589627B2
公开(公告)日：2009-09-15
申请号：US11246900
申请日：2005-10-06
申请人： Nicholas Michael Carbone , Timothy Leo Gallagher , Nishant Kumar , James Laurence Taylor
发明人： Nicholas Michael Carbone , Timothy Leo Gallagher , Nishant Kumar , James Laurence Taylor
IPC分类号： G08B1/08
CPC分类号： H04W8/005 , H04W74/08
摘要： Detecting a wireless device is disclosed. A situation in a wireless medium is created for the wireless device to transmit. A transmission of the wireless device is received. The wireless device is detected based at least in part on information associated with the received transmission of the wireless device.
摘要翻译：公开了检测无线设备。创建无线介质中的情况以使无线设备进行传输。收到无线设备的传输。至少部分地基于与所接收的无线设备的传输相关联的信息来检测无线设备。

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