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1. 发明授权

US5633034A Process for forming a circuit assembly 失效
标题翻译：用于形成电路组件的工艺
公开(公告)号：US5633034A
公开(公告)日：1997-05-27
申请号：US645019
申请日：1996-05-09
申请人： Kenneth R. Carter , Richard A. DiPietro , James L. Hedrick , John P. Hummel , Robert D. Miller , Martha I. Sanchez , Willi Volksen , Do Y. Yoon
发明人： Kenneth R. Carter , Richard A. DiPietro , James L. Hedrick , John P. Hummel , Robert D. Miller , Martha I. Sanchez , Willi Volksen , Do Y. Yoon
IPC分类号： C08G73/10 , H01L23/498 , H01L23/532 , H05K1/00 , H05K1/03 , B05D5/12 , C08G69/14
CPC分类号： H01L23/49894 , C08G73/1007 , C08G73/1039 , H01L23/5329 , H01L2924/0002 , H01L2924/09701 , H05K1/0346 , H05K3/4676
摘要： The invention relates to a process for forming a circuit assembly comprising (i) coating onto a substrate a layer of polyamic ester selected from a unique class of polyamic esters; (ii) imidizing the polyamic ester to form a layer of polyimide having an even surface and (iii) forming circuit conductors on the even surface of the polyimide.
摘要翻译：本发明涉及一种用于形成电路组件的方法，其包括（i）在基底上涂布选自独特类聚酰胺酯的聚酰胺酯层; （ii）酰亚胺化聚酰胺酯以形成具有均匀表面的聚酰亚胺层，和（iii）在聚酰亚胺的均匀表面上形成电路导体。

2. 发明授权

US07097777B2 Magnetic switching device 失效
标题翻译：磁性开关装置
公开(公告)号：US07097777B2
公开(公告)日：2006-08-29
申请号：US11070856
申请日：2005-03-02
申请人： Gregory Costrini , John P. Hummel , George Stojakovic , Kia-Seng Low
发明人： Gregory Costrini , John P. Hummel , George Stojakovic , Kia-Seng Low
IPC分类号： B44C1/22
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , H01F41/308 , H01L43/12
摘要： A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.
摘要翻译：提供一种形成磁性开关装置的方法。该方法包括沉积双层硬掩模，其可以包括氮化钛的第一掩模层和形成在其上的钨的第二掩模层。执行第一光刻处理以对第二掩模层进行图案化，并且执行第二光刻处理以对第一掩模层进行图案化。此后，根据第一掩模层可以对磁性隧道结堆叠进行构图。可以执行蚀刻工艺以根据第二掩模层进一步图案化第一掩模层。可以在第一掩模层和第二掩模层上形成可选的钝化层。

3. 发明授权

US06933204B2 Method for improved alignment of magnetic tunnel junction elements 有权
标题翻译：改善磁性隧道结元件对准的方法
公开(公告)号：US06933204B2
公开(公告)日：2005-08-23
申请号：US10605604
申请日：2003-10-13
申请人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
发明人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
IPC分类号： G03F9/00 , H01L21/76 , H01L23/544 , H01L27/22
CPC分类号： H01L27/222 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.
摘要翻译：用于对准半导体结构中的不透明有源器件的方法包括在形成在下金属化层上的光学透明层上形成不透明层，所述下金属化层包括其中形成的一个或多个对准标记。对应于下部金属化水平中的一个或多个对准标记的位置，对不透明层的一部分进行图案化和打开，以便使一个或多个对准标记光学可见。然后使用光学可见的一个或多个对准标记，相对于较低的金属化水平对不透明层进行图案化。

4. 发明授权

US06551924B1 Post metalization chem-mech polishing dielectric etch 失效
标题翻译：后金属化化学抛光电介质蚀刻
公开(公告)号：US06551924B1
公开(公告)日：2003-04-22
申请号：US09432683
申请日：1999-11-02
申请人： Timothy J. Dalton , John P. Hummel
发明人： Timothy J. Dalton , John P. Hummel
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76885
摘要： A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper. Recipes for simultaneously forming the passivating layer and etching the dielectric layer, and for removing the passivating layer without damaging the underlying conducting and liner layers are provided.
摘要翻译：一种用于蚀刻绝缘层而不损坏绝缘层内的导电层和相关衬里层的方法。介电层沉积在半导体衬底上，然后构图。然后在图案化的电介质中沉积衬垫层和导电层。在通过化学机械抛光平面化导电层之后，在导电层的顶部上沉积钝化层，同时通过不损坏下面的导电层和衬层的工艺同时蚀刻介电层。绝缘层优选是诸如二氧化硅的电介质，并且衬垫层是钽，氮化钽或两者的组合。钝化层优选由以各种化学形式结合的碳和氟组成。导电层优选由铜组成。提供了用于同时形成钝化层和蚀刻介电层以及用于去除钝化层而不损坏下面的导电层和衬层的配方。

5. 发明授权

US08247905B2 Formation of vertical devices by electroplating 有权
标题翻译：通过电镀形成垂直装置
公开(公告)号：US08247905B2
公开(公告)日：2012-08-21
申请号：US12538782
申请日：2009-08-10
申请人： Hariklia Deligianni , Qiang Huang , John P. Hummel , Lubomyr T. Romankiw , Mary B. Rothwell
发明人： Hariklia Deligianni , Qiang Huang , John P. Hummel , Lubomyr T. Romankiw , Mary B. Rothwell
IPC分类号： H01L29/40
CPC分类号： H01L21/76879 , H01L21/2885 , Y10S205/925
摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
摘要翻译：本发明涉及通过电镀形成垂直导电结构的方法。具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构延伸穿过ILD层到分立的金属接触垫上。接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

6. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

7. 发明申请

US20080211055A1 Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit 审中-公开
标题翻译：利用侧壁间隔件在集成电路中形成磁隧道结
公开(公告)号：US20080211055A1
公开(公告)日：2008-09-04
申请号：US12120915
申请日：2008-05-15
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
IPC分类号： H01L43/00 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译：描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

8. 发明授权

US06727589B2 Dual damascene flowable oxide insulation structure and metallic barrier 有权
标题翻译：双镶嵌可流动氧化物绝缘结构和金属屏障
公开(公告)号：US06727589B2
公开(公告)日：2004-04-27
申请号：US09725862
申请日：2000-11-30
申请人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/7684
摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.
摘要翻译：一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面，导电二级保护层。在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。然后重复步骤以获得可比较的镶嵌结构。材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

9. 发明授权

US06593660B2 Plasma treatment to enhance inorganic dielectric adhesion to copper 有权
标题翻译：等离子体处理以增强与铜的无机介电粘附
公开(公告)号：US06593660B2
公开(公告)日：2003-07-15
申请号：US09866937
申请日：2001-05-29
申请人： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
发明人： Leena P. Buchwalter , Barbara Luther , Paul D. Agnello , John P. Hummel , Terence Lawrence Kane , Dirk Karl Manger , Paul Stephen McLaughlin , Anthony Kendall Stamper , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/3185 , H01L21/0445 , H01L21/76801 , H01L21/76807 , H01L21/76834
摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.
摘要翻译：本发明利用还原等离子体处理步骤来增强后续沉积的无机阻挡膜对铜线的粘附，或通过存在于诸如双镶嵌结构的半导体互连结构中。在所述铜线或通孔与无机阻挡膜之间形成包括作为必需元素的Cu，Si和O的材料层的互连结构。

10. 发明授权

US06348736B1 In situ formation of protective layer on silsesquioxane dielectric for dual damascene process 有权
标题翻译：在双镶嵌工艺中在倍半硅氧烷电介质上原位形成保护层
公开(公告)号：US06348736B1
公开(公告)日：2002-02-19
申请号：US09429257
申请日：1999-10-29
申请人： Vincent J. McGahay , John P. Hummel , Joyce Liu , Rebecca Mih , Kamalesh Srivastava , Robert Cook , Stephen E. Greco
发明人： Vincent J. McGahay , John P. Hummel , Joyce Liu , Rebecca Mih , Kamalesh Srivastava , Robert Cook , Stephen E. Greco
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/02134 , H01L21/02137 , H01L21/0234 , H01L21/02362 , H01L21/31144 , H01L21/3122 , H01L21/3124 , H01L21/76807
摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.
摘要翻译：抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。在电介质材料上原位形成第一保护层，例如通过将材料暴露于含氧或含氟的等离子体中。此外，通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或从电介质材料释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多个可能损坏可流动的氧化物材料的其他材料。第一保护层和表面保护层可以通过基本相同的方法形成。因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

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