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1. 发明申请

US20050040893A1 Spectrum profile control for a PLL and the like 有权
公开(公告)号：US20050040893A1
公开(公告)日：2005-02-24
申请号：US10644362
申请日：2003-08-20
申请人： Kenneth Paist , Parag Parikh
发明人： Kenneth Paist , Parag Parikh
IPC分类号： H03K21/00 , H03L7/00 , H03L7/089 , H03L7/197
CPC分类号： H03L7/1976 , H03L7/0891 , H03L7/197
摘要： Frequency spectrum spreading of a timing recovery circuit, such as a PLL, is controlled by periodically calculating each value for a divisor, M, of a fractional divider in the feedback path of the PLL. The fractional divider divides the output signal of a voltage-controlled oscillator (VCO) of the PLL by the divisor, M, and the value for divisor, M, is periodically updated based on a spreading profile. The output of the fractional divider and a reference clock signal are provided to a phase detector of the PLL so as to cause the PLL to slew the output frequency of the PLL in accordance with the spreading profile.

2. 发明授权

US08422536B2 Spread spectrum clock signal generator method and system 有权
标题翻译：扩频时钟信号发生器的方法和系统
公开(公告)号：US08422536B2
公开(公告)日：2013-04-16
申请号：US12774175
申请日：2010-05-05
申请人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
发明人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B1/69
CPC分类号： H04B1/69 , H03B23/00
摘要： A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.
摘要翻译：一种用于产生具有作为重复数的函数的常数ppm偏移的扩频时钟信号的系统和方法。可以与锁相环电路相关联地配置相位插值器，以便提供由PLL电路产生的位时钟的相位移动。重复数字分频器计算分段SSC调制曲线中每个时隙的重复数。可以采用噪声整形调制器来调制与重复数相关联的分数部分。重复计数器和相位累加器接收重复数的整数部分，并且计数等于整数和重复数的Σ-Δ调制小数部分之和的单位间隔时钟周期。相位累加器可以根据扩频方向的符号递增和/或递减。

3. 发明申请

US20050168290A1 Clock generation circuits providing slewing of clock frequency 有权
标题翻译：时钟发生电路提供时钟频率的回转
公开(公告)号：US20050168290A1
公开(公告)日：2005-08-04
申请号：US10770046
申请日：2004-02-02
申请人： Parag Parikh
发明人： Parag Parikh
IPC分类号： H03L7/00 , H03L7/099 , H03L7/18
CPC分类号： H03L7/18 , H03L7/0996
摘要： Techniques are described for slewing a clock frequency of a clock signal from an initial clock frequency to a final clock frequency. An oscillator provides a number of phase outputs. A current frequency divider value is set to an initial frequency divider value, the initial frequency divider value corresponding to the initial clock frequency. A period of a feedback signal is modified through a number of periods from an initial period to a final period, utilizing one or more of the phase outputs. The current frequency divider value is changed when the period of the feedback signal reaches the final period. The modify and change operations are performed until the current frequency divider value reaches a final frequency divider value, where the final frequency divider value corresponds to the final clock frequency.
摘要翻译：描述了将时钟信号的时钟频率从初始时钟频率转换到最终时钟频率的技术。振荡器提供多个相位输出。当前分频器值被设置为初始分频器值，初始分频器值对应于初始时钟频率。通过使用一个或多个相位输出，从初始周期到最后周期的多个周期来修改反馈信号的周期。当反馈信号的周期达到最后期间时，当前的分频器值被改变。执行修改和改变操作，直到当前分频器值达到最终分频器值，其中最终分频器值对应于最终时钟频率。

4. 发明申请

US20110274143A1 SPREAD SPECTRUM CLOCK SIGNAL GENERATOR METHOD AND SYSTEM 有权
标题翻译：传播频谱信号发生器方法和系统
公开(公告)号：US20110274143A1
公开(公告)日：2011-11-10
申请号：US12774175
申请日：2010-05-05
申请人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
发明人： Joseph Anidjar , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B1/69 , H03D3/24
CPC分类号： H04B1/69 , H03B23/00
摘要： A system and method for generating a spread spectrum clock signal with a constant ppm offset as a function of a repetition number. A phase interpolator can be configured in association with of a phase-locked loop circuit in order to provide a phase movement from a bit clock generated by the PLL circuit. A repetition number divider computes the repetition number for each time slot in a piece-wise SSC modulation profile. A noise shaping modulator can be employed for modulating a fractional part associated with the repetition number. A repetition counter and a phase accumulator receives an integer part of the repetition number and counts unit interval clock periods equal to a sum of integer and the sigma-delta modulated fractional parts of the repetition number. The phase accumulator can be incremented and/or decremented based on the sign of the spread spectrum direction.
摘要翻译：一种用于产生具有作为重复数的函数的常数ppm偏移的扩频时钟信号的系统和方法。可以与锁相环电路相关联地配置相位插值器，以便提供由PLL电路产生的位时钟的相位移动。重复数字分频器计算分段SSC调制曲线中每个时隙的重复数。可以采用噪声整形调制器来调制与重复数相关联的分数部分。重复计数器和相位累加器接收重复数的整数部分，并且计数等于整数和重复数的Σ-Δ调制小数部分之和的单位间隔时钟周期。相位累加器可以根据扩频方向的符号递增和/或递减。

5. 发明授权

US07593831B2 Method and apparatus for testing delay lines 失效
标题翻译：用于测试延迟线的方法和装置
公开(公告)号：US07593831B2
公开(公告)日：2009-09-22
申请号：US11499363
申请日：2006-08-04
申请人： Werner Bachhuber , Osman Doertok , Parag Parikh
发明人： Werner Bachhuber , Osman Doertok , Parag Parikh
IPC分类号： G04F8/00 , H03H11/26
CPC分类号： G01R31/3016
摘要： Disclosed is a circuit for testing a delay module. An output of a ring oscillator formed with the delay module is transmitted to a counter. The counter generates a plurality of counts, each count associated with a setting of control lines of the delay module. One of the plurality of counts is then compared with a previous one of the plurality of counts.
摘要翻译：公开了一种用于测试延迟模块的电路。形成有延迟模块的环形振荡器的输出被发送到计数器。计数器产生多个计数，每个计数与延迟模块的控制线的设置相关联。然后将多个计数中的一个与多个计数中的前一个进行比较。

6. 发明申请

US20080033678A1 Method and apparatus for testing delay lines 失效
标题翻译：用于测试延迟线的方法和装置
公开(公告)号：US20080033678A1
公开(公告)日：2008-02-07
申请号：US11499363
申请日：2006-08-04
申请人： Werner Bachhuber , Osman Doertok , Parag Parikh
发明人： Werner Bachhuber , Osman Doertok , Parag Parikh
IPC分类号： G06F19/00
CPC分类号： G01R31/3016
摘要： Disclosed is a circuit for testing a delay module. An output of a ring oscillator formed with the delay module is transmitted to a counter. The counter generates a plurality of counts, each count associated with a setting of control lines of the delay module. One of the plurality of counts is then compared with a previous one of the plurality of counts.
摘要翻译：公开了一种用于测试延迟模块的电路。形成有延迟模块的环形振荡器的输出被发送到计数器。计数器产生多个计数，每个计数与延迟模块的控制线的设置相关联。然后将多个计数中的一个与多个计数中的前一个进行比较。

7. 发明申请

US20070079165A1 Multi-stage clock selector 失效
标题翻译：多级时钟选择器
公开(公告)号：US20070079165A1
公开(公告)日：2007-04-05
申请号：US11240290
申请日：2005-09-30
申请人： Parag Parikh
发明人： Parag Parikh
IPC分类号： G06F1/06
CPC分类号： H03K5/13
摘要： A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.
摘要翻译：一种时钟选择器，用于从多个输入时钟信号中选择一组候选时钟信号。相位选择器包括适于产生多个控制信号的控制逻辑和由控制信号控制的多个多路复用器，并且布置成具有至少第一级和最后级的两级或更多级。第一级的输入是多个输入时钟信号。至少一个级适于（i）接收多个时钟信号，（ii）至少丢弃所接收的多个时钟信号的第一或最后一个时钟信号，以及（iii）输出减少的多个时钟信号。最后一级的输出是候选时钟信号的集合。

8. 发明申请

US20120287983A1 METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES 有权
标题翻译：用于串行器/ DESERIALIZER器件中接收路径的异常异步测试的方法和装置
公开(公告)号：US20120287983A1
公开(公告)日：2012-11-15
申请号：US13558794
申请日：2012-07-26
申请人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
发明人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B17/00
CPC分类号： H04L1/24 , H03L7/087 , H03M9/00
摘要： Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.
摘要翻译：提供了串行器/解串器（SerDes）器件中的接收路径的伪异步测试的方法和装置。在测试模式期间，通过将串行数据源应用于SerDes设备的接收路径来测试SerDes设备。接收路径基本上与使用位时钟的输入数据对准。在相对于串行数据源的位时钟的测试模式期间调整相位以评估SerDes器件。串行数据的源可以是例如由锁相环使用以产生位时钟的参考时钟。比特时钟的相位可以在测试模式期间直接控制，例如通过测试相位控制信号，例如施加到改变比特时钟的相位的内插器的多个内插码。

9. 发明授权

US08275025B2 Methods and apparatus for pseudo asynchronous testing of receive path in serializer/deserializer devices 有权
标题翻译：串行器/解串器设备中接收路径伪异步测试的方法和装置
公开(公告)号：US08275025B2
公开(公告)日：2012-09-25
申请号：US12394286
申请日：2009-02-27
申请人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
发明人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B17/00
CPC分类号： H04L1/24 , H03L7/087 , H03M9/00
摘要： Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.
摘要翻译：提供了串行器/解串器（SerDes）器件中的接收路径的伪异步测试的方法和装置。在测试模式期间，通过将串行数据源应用于SerDes设备的接收路径来测试SerDes设备。接收路径基本上与使用位时钟的输入数据对准。在相对于串行数据源的位时钟的测试模式期间调整相位以评估SerDes器件。串行数据的源可以是例如由锁相环使用以产生位时钟的参考时钟。比特时钟的相位可以在测试模式期间直接控制，例如通过测试相位控制信号，例如施加到改变比特时钟的相位的内插器的多个内插码。

10. 发明申请

US20100220776A1 METHODS AND APPARATUS FOR PSEUDO ASYNCHRONOUS TESTING OF RECEIVE PATH IN SERIALIZER/DESERIALIZER DEVICES 有权
标题翻译：用于串行器/ DESERIALIZER器件中接收路径的异常异步测试的方法和装置
公开(公告)号：US20100220776A1
公开(公告)日：2010-09-02
申请号：US12394286
申请日：2009-02-27
申请人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
发明人： Christopher J. Abel , Parag Parikh , Vladimir Sindalovsky
IPC分类号： H04B17/00
CPC分类号： H04L1/24 , H03L7/087 , H03M9/00
摘要： Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.
摘要翻译：提供了串行器/解串器（SerDes）器件中的接收路径的伪异步测试的方法和装置。在测试模式期间，通过将串行数据源应用于SerDes设备的接收路径来测试SerDes设备。接收路径基本上与使用位时钟的输入数据对准。在相对于串行数据源的位时钟的测试模式期间调整相位以评估SerDes器件。串行数据的源可以是例如由锁相环使用以产生位时钟的参考时钟。比特时钟的相位可以在测试模式期间直接控制，例如通过测试相位控制信号，例如施加到改变比特时钟的相位的内插器的多个内插码。

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