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1. 发明授权

US5630097A Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses 失效
标题翻译：增强的缓存操作，重新映射页面，以优化从导致高速缓存未命中的地址的数据重定位
公开(公告)号：US5630097A
公开(公告)日：1997-05-13
申请号：US178487
申请日：1994-01-07
申请人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
发明人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
IPC分类号： G06F12/08 , G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F12/0864 , G06F2212/653
摘要： A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The primary feature of the invention is to add bus activity sampling logic to the CPU and enhance the operating system to allow the operating system to detect when cache thrashing is occurring and remap data pages to new physical memory locations to eliminate the cache thrashing situation.
摘要翻译：执行虚拟存储器管理并具有高速缓存的计算机系统以通过重新映射检测到高速缓存未命中的物理存储器的页面来减少高速缓存未命中的方式操作。该方法包括检测高速缓存未命中，如通过观察系统总线上的高速缓存填充操作，然后重新映射主存储器中包含最频繁高速缓存未命中的地址的页面，使得引起颠簸的存储器引用可以在不同的页面中共存的缓存。对于执行虚拟存储器操作系统的CPU，可以通过简单地更新页面映射表来反映页面的新的物理位置，将一页数据或指令移动到不同的物理页面帧，但保持在相同的虚拟地址，并将数据从旧页框复制到新页。本发明的主要特征是将总线活动采样逻辑添加到CPU并增强操作系统以允许操作系统检测何时发生高速缓存抖动，并将数据页重新映射到新的物理存储器位置以消除高速缓存抖动情况。

2. 发明授权

US5237673A Memory management method for coupled memory multiprocessor systems 失效
标题翻译：耦合存储器多处理器系统的内存管理方法
公开(公告)号：US5237673A
公开(公告)日：1993-08-17
申请号：US673132
申请日：1991-03-20
申请人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
发明人： David A. Orbits , Kenneth D. Abramson , H. Bruce Butts, Jr.
IPC分类号： G06F12/08
CPC分类号： G06F12/08
摘要： A method of managing the memory of a CM multiprocessor computer system is disclosed. A CM multiprocessor computer system includes: a plurality of CPU modules 11a . . . 11n to which processes are assigned; one or more optional global memories 13a . . . 13n; a storage medium 15a, 15b . . . 15n; and a global interconnect 12. Each of the CPU modules 11a . . . 11n includes a processor 21 and a coupled memory 23 accessible by the local processor without using the global interconnect 12. Processors have access to remote coupled memory regions via the global interconnect 12. Memory is managed by transferring, from said storage medium, the data and stack pages of a process to be run to the coupled memory region of the CPU module to which the process is assigned, when the pages are called for by the process. Other pages are transferred to global memory, if available. At prescribed intervals, the free memory of each coupled memory region and global memory is evaluated to determine if it is below a threshold. If below the threshold, a predetermined number of pages of the memory region are scanned. Infrequently used pages are placed on the end of a list of pages that can be replaced with pages stored in the storage medium. Pages associated with processes that are terminating are placed at the head of the list of replacement pages.
摘要翻译：公开了一种管理CM多处理器计算机系统的存储器的方法。 CM多处理器计算机系统包括：多个CPU模块11a。。。 11n分配进程; 一个或多个可选全局存储器13a。。。 13n; 存储介质15a，15b。。。 15n; 和全局互连12.每个CPU模块11a。。。 11n包括处理器21和可由本地处理器访问的耦合存储器23，而不使用全局互连12.处理器可经由全局互连12访问远程耦合的存储器区域。存储器通过从所述存储介质传送数据和当进程调用页面时，要运行到进程分配到的CPU模块的耦合存储器区域的进程的堆叠页面。其他页面将传输到全局内存（如果可用）。以规定的间隔，评估每个耦合的存储器区域和全局存储器的空闲存储器以确定其是否低于阈值。如果低于阈值，则扫描存储区域的预定页数。不经常使用的页面放置在可以用存储介质中存储的页面替换的页面列表的末尾。与正在终止的进程关联的页面被放置在替换页面列表的头部。

3. 发明授权

US5506987A Affinity scheduling of processes on symmetric multiprocessing systems 失效
标题翻译：对称多处理系统上进程的亲和度调度
公开(公告)号：US5506987A
公开(公告)日：1996-04-09
申请号：US217127
申请日：1994-03-24
申请人： Kenneth D. Abramson , H. Bruce Butts, Jr. , David A. Orbits
发明人： Kenneth D. Abramson , H. Bruce Butts, Jr. , David A. Orbits
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F9/5033
摘要： A method of scheduling processes on a symmetric multiprocessing system that maintains process-to-CPU affinity without introducing excessive idle time is disclosed. When a new process is assigned, the process is identified as young and small, given a migtick value and assigned to a specific CPU. If the priority of a process placed on a run queue is above a threshold, the high priority count of the assigned CPU is incremented. At predetermined clock intervals, an interrupt occurs that causes the migtick value of running processes to be decremented. Then each CPU is tested to determine if its high priority count is greater than zero. CPUs having high priority counts greater than zero are tested to determine if any processes having a priority greater than the priority of the running process are assigned. If higher priority processes are assigned to a CPU having assigned processes lying above the threshold, a context switch takes place that results in the higher priority process being run. At regular intervals, a migration deamon is run to load balance the multiprocessor system. First, a large/small process threshold is determined. Then processes whose migtick values are below a migtick threshold (e.g., 0) are identified as old. Old processes then are identified as large or small processes based on their memory usage. Next, a determination is made of whether the small and large process load balances of the system can be improved. If either or both can be improved, the smallest small and/or the smallest large processes are migrated from their assigned CPU to the CPU with, as the case may be, the least large or the least small processes.
摘要翻译：公开了一种在不引入过多空闲时间的情况下在维持进程到CPU之间关联的对称多处理系统上调度进程的方法。当分配新进程时，该进程被识别为年轻和小型，给定一个迁移值并分配给特定的CPU。如果放置在运行队列上的进程的优先级高于阈值，则分配的CPU的高优先级计数将增加。在预定的时钟间隔，发生中断运行进程的迁移值减少的中断。然后测试每个CPU以确定其高优先级计数是否大于零。测试具有大于零的高优先级计数的CPU以确定是否分配了优先级大于运行进程的优先级的任何进程。如果将较高优先级的进程分配给具有高于阈值的分配的进程的CPU，则会进行上下文切换，从而导致更高优先级的进程正在运行。定期运行迁移设计以负载平衡多处理器系统。首先，确定大/小的过程阈值。然后，其迁移值低于迁移阈值（例如，0）的进程被识别为旧。然后，旧的进程将根据其内存使用情况识别为大型或小型进程。接下来，确定是否可以提高系统的小型和大型过程负载平衡。如果可以改进这两者之一，则最小的小型和/或最小的大型进程将从其分配的CPU迁移到CPU（视情况而定）最小或最小的进程。

4. 发明授权

US5303362A Coupled memory multiprocessor computer system including cache coherency management protocols 失效
标题翻译：耦合存储器多处理器计算机系统包括高速缓存一致性管理协议
公开(公告)号：US5303362A
公开(公告)日：1994-04-12
申请号：US673766
申请日：1991-03-20
申请人： H. Bruce Butts, Jr. , David A. Orbits , Kenneth D. Abramson
发明人： H. Bruce Butts, Jr. , David A. Orbits , Kenneth D. Abramson
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21); cache memory (23); cache memory controller logic (22); coupled memory (25); coupled memory control logic (24); and a global interconnect interface (27). Coupled memory (25) associated with a specific processor (21), like global memory (15), is available to other processors (21). Coherency between data stored in coupled (or global) memory and similar data replicated in cache memory is maintained by either a write-through or a write-back cache coherency management protocol. The selected protocol is implemented in hardware, i.e., logic, form, preferably incorporated in the coupled memory control logic (24) and in the cache memory controller logic (22). In the write-through protocol, processor writes are propagated directly to coupled memory while invalidating corresponding data in cache memory. In contrast, the write-back protocol allows data owned by a cache to be continuously updated until requested by another processor, at which time the coupled memory is updated and other cache blocks containing the same data are invalidated.
摘要翻译：公开了一种包括多个处理器模块（11a，11b ...），全局互连（13），可选全局存储器（15）和输入/输出子系统（17,19）的相干耦合存储器多处理器计算机系统。每个处理器模块（11a，11b ...）包括：处理器（21）; 缓存存储器（23）; 缓存存储器控制器逻辑（22）; 耦合存储器（25）; 耦合存储器控制逻辑（24）; 和全局互连接口（27）。与诸如全局存储器（15）的特定处理器（21）相关联的耦合存储器（25）可用于其他处理器（21）。存储在耦合（或全局）存储器中的数据与在高速缓冲存储器中复制的类似数据之间的一致性通过写通或回写高速缓存一致性管理协议进行维护。所选择的协议以硬件（即，逻辑形式）实现，优选地并入耦合的存储器控制逻辑（24）和高速缓存存储器控制器逻辑（22）中。在直写协议中，处理器写入直接传播到耦合的存储器，同时使高速缓冲存储器中的对应数据无效。相比之下，回写协议允许持续更新高速缓存所拥有的数据，直到另一个处理器请求，此时更新耦合的存储器，并且包含相同数据的其他缓存块无效。

5. 发明授权

US5269013A Adaptive memory management method for coupled memory multiprocessor systems 失效
标题翻译：耦合存储器多处理器系统的自适应存储器管理方法
公开(公告)号：US5269013A
公开(公告)日：1993-12-07
申请号：US674077
申请日：1991-03-20
申请人： Kenneth D. Abramson , David A. Orbits , H. Bruce Butts, Jr.
发明人： Kenneth D. Abramson , David A. Orbits , H. Bruce Butts, Jr.
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/08
摘要： An adaptive memory management method for coupled memory multiprocessor computer systems is disclosed. In a coupled memory multiprocessor system all the data and stack pages of processes assigned to individual multiprocessors are, preferably, located in a memory region coupled to the assigned processor. When this becomes impossible, some data and stack pages are assigned to global memory or memory regions coupled to other processors. The present invention is a method of making certain that the most referenced data and stack pages are located in the coupled memory of the processor to which a specific process is assigned and lesser referenced pages are located in global memory or the coupled memory region of other processors. This result is accomplished by sampling the memory references made by the processors of the computer system and causing the most recently referenced pages in each coupled memory region to be maintained at the head of an active page list. References to remote data and stack pages are stored in a remote page hash table. Remote pages are pages stored in global memory or in coupled memory other than the coupled memory of the processor to which the process owning the pages is assigned. Any remote data and stack pages referenced more frequently than pages stored in a processor's coupled memory region are transferred to the processor's coupled memory region. If a processor's coupled memory region is tight, pages are transferred from the processor's coupled memory region to global memory or to the coupled memory region of another processor.
摘要翻译：公开了一种用于耦合存储器多处理器计算机系统的自适应存储器管理方法。在耦合存储器多处理器系统中，分配给各个多处理器的所有进程的数据和堆栈页面优选地位于耦合到所分配的处理器的存储器区域中。当这不可能时，一些数据和堆栈页面被分配给耦合到其他处理器的全局存储器或存储器区域。本发明是确定最引用的数据和堆栈页面位于处理器的耦合存储器中的方法，处理器的特定处理被分配到该存储器中，并且较小的参考页面位于全局存储器或其他处理器的耦合存储器区域中。该结果通过对由计算机系统的处理器进行的存储器引用进行采样并使得每个耦合的存储器区域中最近被引用的页面被维护在活动页面列表的头部来实现。对远程数据和堆栈页的引用存储在远程页哈希表中。远程页面是存储在全局存储器中的页面，或存储有分配了页面的进程的处理器的耦合存储器之外的耦合存储器中的页面。比存储在处理器的耦合存储器区域中的页面更频繁地引用的任何远程数据和堆栈页面被传送到处理器的耦合存储器区域。如果处理器的耦合存储器区域紧密，则页面从处理器的耦合存储器区域传送到全局存储器或另一个处理器的耦合存储器区域。

6. 发明授权

US5383370A Device for verifying a minimum torque value 失效
标题翻译：用于验证最小扭矩值的装置
公开(公告)号：US5383370A
公开(公告)日：1995-01-24
申请号：US682638
申请日：1991-04-09
申请人： Kenneth D. Abramson , Tetsuo Abe
发明人： Kenneth D. Abramson , Tetsuo Abe
IPC分类号： B23P19/06 , G01L5/00 , G01L3/10
CPC分类号： G01L5/0042
摘要： A device for verifying or measuring a minimum value of a previously applied torque on a workpiece such as bolt, nut, etc., includes a motor, a reduction gear assembly, a torque transducer and a fastener engaging member, including a rotatably spindle. The motor causes the spindle to rotate. A torsion bar interposed the spindle and the motor absorbs the inertia of the motor when the motor is stopped to minimize torque overshoot, as well as taking up the rotation generated by the motor immediately upon engagement with a workpiece. An angle encoder senses any rotation of the workpiece caused by the rotation of the spindle. Any rotation of the workpiece means that the previously applied torque is below a minimum predetermined value.
摘要翻译：用于验证或测量诸如螺栓，螺母等的工件上的先前施加的扭矩的最小值的装置包括电动机，减速齿轮组件，扭矩传感器和紧固件接合构件，包括可旋转的主轴。电机使主轴旋转。插入主轴和马达的扭杆在电机停止时吸收马达的惯性，以最小化扭矩过冲，以及在与工件接合时马达产生的旋转。角度编码器感测由主轴的旋转引起的工件的任何旋转。工件的任意旋转意味着先前施加的转矩低于最小预定值。

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