会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US20100034039A1
    • 2010-02-11
    • US12458428
    • 2009-07-13
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • G11C7/00
    • G11C7/1033G06F11/1044G11C7/08G11C11/4091
    • A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.
    • 半导体集成电路具有耦合到相同字线的存储器单元数量K(K是2个或更多个的自然数),以及耦合到存储单元的多个读出放大器电路。 多个读出放大器电路分为N个(N个是2个以上的自然数)组。 在N个组中,在第一组读出放大器电路被激活并执行预定的读出操作之后,激活第二组读出放大器电路并执行预定的读出操作, 读出放大器电路的第N组顺序地被激活,以执行预定的读出操作。
    • 3. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08310297B2
    • 2012-11-13
    • US12929753
    • 2011-02-14
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • H03K3/01
    • H03K5/05H01L2924/0002H03K3/0375H03K3/356156H03K2005/00058H01L2924/00
    • Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
    • 公开了一种半导体器件,包括:模式控制电路,当待机控制信号处于激活状态时,基于来自定时器电路的定时器输出信号,生成改变功能电路部分的逻辑状态的MODE控制输出信号 以及输出控制电路,其接收所述功能电路部的输出信号,并控制所述输出信号的输出; 基于通过延迟电路延迟MODE控制输出信号而产生的延迟输出信号。 当功能电路部分通过MODE控制输出信号改变逻辑状态时,输出控制电路不将功能电路部分输出信号传送到输出,而是在功能电路部分变化之前保持并输出功能电路部分输出信号 逻辑状态由MODE控制输出信号。
    • 5. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08552793B2
    • 2013-10-08
    • US13620803
    • 2012-09-15
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • H03K3/01
    • H03K5/05H01L2924/0002H03K3/0375H03K3/356156H03K2005/00058H01L2924/00
    • A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.
    • 一种半导体集成电路装置,具备包含多个场效应晶体管的功能电路部,模式控制电路,接收第一控制信号,生成用于改变功能电路部的逻辑状态的第二控制信号, 输出控制电路,其接收功能电路部分的输出信号并控制输出信号的输出;以及控制电路,其接收第二控制信号并向输出控制电路产生第三控制信号。 在功能电路部分根据第二控制信号改变逻辑状态的时间段期间,输出控制电路根据第三控制信号反转功能电路部分的输出信号。
    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20130033308A1
    • 2013-02-07
    • US13620803
    • 2012-09-15
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • H01L25/00
    • H03K5/05H01L2924/0002H03K3/0375H03K3/356156H03K2005/00058H01L2924/00
    • A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.
    • 一种半导体集成电路装置,具备包含多个场效应晶体管的功能电路部,模式控制电路,接收第一控制信号,生成用于改变功能电路部的逻辑状态的第二控制信号, 输出控制电路,其接收功能电路部分的输出信号并控制输出信号的输出;以及控制电路,其接收第二控制信号并向输出控制电路产生第三控制信号。 在功能电路部分根据第二控制改变逻辑状态的时间段期间。 信号,输出控制电路根据第三控制信号反转功能电路部分的输出信号。
    • 9. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US08054705B2
    • 2011-11-08
    • US12458428
    • 2009-07-13
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • G11C7/06
    • G11C7/1033G06F11/1044G11C7/08G11C11/4091
    • A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.
    • 半导体集成电路具有耦合到相同字线的存储器单元数量K(K是2个或更多个的自然数),以及耦合到存储单元的多个读出放大器电路。 多个读出放大器电路分为N个(N个是2个以上的自然数)组。 在N个组中,在第一组读出放大器电路被激活并执行预定的读出操作之后,激活第二组读出放大器电路并执行预定的读出操作, 读出放大器电路的第N组顺序地被激活,以执行预定的读出操作。
    • 10. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20110199140A1
    • 2011-08-18
    • US12929753
    • 2011-02-14
    • Kenjyu ShimogawaHiroshi Furuta
    • Kenjyu ShimogawaHiroshi Furuta
    • H03K3/356
    • H03K5/05H01L2924/0002H03K3/0375H03K3/356156H03K2005/00058H01L2924/00
    • Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.
    • 公开了一种半导体器件,包括:模式控制电路,当待机控制信号处于激活状态时,基于来自定时器电路的定时器输出信号,生成改变功能电路部分的逻辑状态的MODE控制输出信号 以及输出控制电路,其接收所述功能电路部的输出信号,并控制所述输出信号的输出; 基于通过延迟电路延迟MODE控制输出信号而产生的延迟输出信号。 当功能电路部分通过MODE控制输出信号改变逻辑状态时,输出控制电路不将功能电路部分输出信号传送到输出,而是在功能电路部分变化之前保持并输出功能电路部分输出信号 逻辑状态由MODE控制输出信号。