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1. 发明授权

US06980043B2 Ferroelectric element and a ferroelectric gate device using the same 有权
标题翻译：铁电元件和使用其的铁电栅极器件
公开(公告)号：US06980043B2
公开(公告)日：2005-12-27
申请号：US11052794
申请日：2005-02-09
申请人： Kenji Toyoda , Takashi Ohtsuka
发明人： Kenji Toyoda , Takashi Ohtsuka
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/866 , H03K17/62
CPC分类号： G11C11/22
摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1) comprises is applied to said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).
摘要翻译：一种铁电栅极器件，包括铁电电容器（1），用作电阻器的开关元件（2）或取决于所施加的电压的电容器;以及具有源极，漏极和栅极的场效应晶体管所述铁电电容器（1）的一端具有输入端（IN），所述铁电电容器（1）的另一端与所述开关元件（2）的一端连接，所述开关元件（2）的另一端）通过向所述输入端子施加电压而连接到所述场效应晶体管（6）的栅极，所述开关元件（2）在高于铁电体的矫顽电压（Vc）的电压时用作电阻器所述铁电电容器（1）包括的所述铁电电容器（1）被施加到所述铁电电容器（1），并且通过向所述输入端子施加电压，所述开关元件（2）当电压低于所述铁电电容器（1）的矫顽电压说ferroelec 三体物质被施加到所述铁电电容器（1）。

2. 发明授权

US06949780B2 Semiconductor device 有权
公开(公告)号：US06949780B2
公开(公告)日：2005-09-27
申请号：US10847323
申请日：2004-05-18
申请人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
发明人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
IPC分类号： H01L27/10 , G11C27/00 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C27/005 , G11C11/54 , H01L2924/0002 , H01L2924/00
摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

3. 发明授权

US06859088B2 Ferroelectric element and a ferroelectric gate device using the same 有权
标题翻译：铁电元件和使用其的铁电栅极器件
公开(公告)号：US06859088B2
公开(公告)日：2005-02-22
申请号：US10716670
申请日：2003-11-20
申请人： Kenji Toyoda , Takashi Ohtsuka
发明人： Kenji Toyoda , Takashi Ohtsuka
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/866 , H03K17/62 , H03K17/687
CPC分类号： G11C11/22
摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor of a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).
摘要翻译：一种强电介质栅极器件，包括铁电电容器（1），根据施加的电压用作电容器的电阻器的开关元件（2）和具有源极，漏极和栅极的场效应晶体管所述铁电电容器（1）的一端具有输入端（IN），所述铁电电容器（1）的另一端与所述开关元件（2）的一端连接，所述开关元件（2）的另一端）通过向所述输入端子施加电压而连接到所述场效应晶体管（6）的栅极，所述开关元件（2）在高于铁电体的矫顽电压（Vc）的电压时用作电阻器所述铁电电容器（1），并且当低于所述铁电体的矫顽电压（Vc）的电压施加到所述铁电电容器时，所述开关元件（2）作为电容器施加电压到所述输入端子， 1）。

4. 发明申请

US20050206421A1 Nonvolatile flip-flop circuit and method of driving the same 有权
标题翻译：非易失性触发电路及其驱动方法
公开(公告)号：US20050206421A1
公开(公告)日：2005-09-22
申请号：US11080454
申请日：2005-03-16
申请人： Takashi Nishikawa , Kenji Toyoda , Takashi Ohtsuka
发明人： Takashi Nishikawa , Kenji Toyoda , Takashi Ohtsuka
IPC分类号： G11C11/22 , H03K3/356 , H03K3/289
CPC分类号： H03K3/356008 , G11C11/22
摘要： The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (−Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor (601).
摘要翻译：本发明提供了一种驱动非易失性触发电路的方法，包括以下步骤：数据保持步骤，当数据信号D（D）被利用时，利用铁电栅极晶体管（601）的铁电材料的极化来保持输入数据信号D 在第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）导通时，第一开关元件（605），第二开关元件（607）和第三开关元件时钟反相器（608）关闭; 以及数据输出步骤，基于将第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）放置在OFF中的保持数据信号D输出输出信号Q（-Q）状态，并且将第一开关元件（605），第二开关元件（607）和第三时钟反相器（608）置于导通状态，以便中断数据信号的输入并保持铁电材料的极化状态的铁电栅极晶体管（601）。

5. 发明申请

US20050146917A1 Ferroelectric element and a ferroelectric gate device using the same 有权
公开(公告)号：US20050146917A1
公开(公告)日：2005-07-07
申请号：US11052794
申请日：2005-02-09
申请人： Kenji Toyoda , Takashi Ohtsuka
发明人： Kenji Toyoda , Takashi Ohtsuka
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105 , H01L29/866 , H03K17/62
CPC分类号： G11C11/22
摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1) comprises is applied to said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).

6. 发明授权

US06844582B2 Semiconductor device and learning method thereof 失效
标题翻译：半导体器件及其学习方法
公开(公告)号：US06844582B2
公开(公告)日：2005-01-18
申请号：US10434358
申请日：2003-05-09
申请人： Michihito Ueda , Kenji Toyoda , Takashi Ohtsuka , Kiyoyuki Morita
发明人： Michihito Ueda , Kenji Toyoda , Takashi Ohtsuka , Kiyoyuki Morita
IPC分类号： G06N3/063 , G11C27/00 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L45/00 , H01L29/76 , H01L27/108 , G06F15/18 , G06G7/00
CPC分类号： H01L27/11502 , G06N3/0635 , G11C11/54 , G11C27/00 , H01L21/84 , H01L27/115 , H01L27/11507 , H01L27/11521 , H01L27/11585 , H01L27/1159 , H01L27/1203 , H01L45/06 , H01L45/1206 , H01L45/144
摘要： A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.
摘要翻译：本发明的半导体器件的学习方法包括具有倍增器作为突触的神经器件，其中重量根据输入重量电压而变化，并且用作处理模拟数据的神经网络系统，其包括步骤A的步骤A 向神经装置输入预定的输入数据并计算神经装置的输出的目标值相对于输入数据与实际输出之间的误差;步骤B，通过改变神经元的重量来计算误差的变化量; 之后的乘法器，以及基于误差变化量来改变乘法器的权重的步骤C，其中在步骤B和C中，在输入用于将权重设定为基本恒定值的复位电压之后，重量电压，通过输入与要变化的重量相对应的重量电压来改变重量。

7. 发明授权

US06990006B2 Non-volatile memory cell and a method of controlling the same 有权
标题翻译：非易失性存储单元及其控制方法
公开(公告)号：US06990006B2
公开(公告)日：2006-01-24
申请号：US10829235
申请日：2004-04-22
申请人： Takashi Ohtsuka , Kenji Toyoda
发明人： Takashi Ohtsuka , Kenji Toyoda
IPC分类号： G11C11/22
CPC分类号： G11C14/00 , G11C11/22
摘要： A non-volatile memory cell comprising a latch circuit (1) which comprises a first node (6) and a second node (7) and latches complementary data set in the first node (6) and the second node (7), a first switching element (4) which connects the first node (6) and a first data input/output line (2), a second switching element (5) which connects the second node (7) and a second data input/output line (3), a first ferroelectric capacitor (8a) which connects the second data input/output line (3) and the first node (6), and a second ferroelectric capacitor (8b) which connects the first data input/output line (2) and the second node (7).
摘要翻译：一种包括锁存电路（1）的非易失性存储单元，所述锁存电路包括第一节点（6）和第二节点（7），并锁存所述第一节点（6）和所述第二节点（7）中的互补数据集，第一节点连接第一节点（6）和第一数据输入/输出线（2）的开关元件（4），连接第二节点（7）和第二数据输入/输出线（3）的第二开关元件），连接第二数据输入/输出线（3）和第一节点（6）的第一铁电电容器（8a）和连接第一数据输入/输出线（2）的第二铁电电容器（8b））和第二节点（7）。

8. 发明授权

US07002388B2 Nonvolatile flip-flop circuit and method of driving the same 有权
标题翻译：非易失性触发电路及其驱动方法
公开(公告)号：US07002388B2
公开(公告)日：2006-02-21
申请号：US11080454
申请日：2005-03-16
申请人： Takashi Nishikawa , Kenji Toyoda , Takashi Ohtsuka
发明人： Takashi Nishikawa , Kenji Toyoda , Takashi Ohtsuka
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C11/22
摘要： The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (−Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor (601).
摘要翻译：本发明提供了一种驱动非易失性触发电路的方法，包括以下步骤：数据保持步骤，当数据信号D（D）被利用时，利用铁电栅极晶体管（601）的铁电材料的极化来保持输入数据信号D 在第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）导通时，第一开关元件（605），第二开关元件（607）和第三开关元件时钟反相器（608）关闭; 以及数据输出步骤，基于将第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）放置在OFF中的保持数据信号D输出输出信号Q（-Q）状态，并且将第一开关元件（605），第二开关元件（607）和第三时钟反相器（608）置于导通状态，以便中断数据信号的输入并保持铁电材料的极化状态的铁电栅极晶体管（601）。

9. 发明授权

US06862226B2 Method of driving a non-volatile flip-flop circuit using variable resistor elements 有权
标题翻译：使用可变电阻元件驱动非易失性触发器电路的方法
公开(公告)号：US06862226B2
公开(公告)日：2005-03-01
申请号：US10784257
申请日：2004-02-24
申请人： Kenji Toyoda , Takashi Ohtsuka
发明人： Kenji Toyoda , Takashi Ohtsuka
IPC分类号： G11C14/00 , H01L27/10 , H03K3/356 , G11C11/00
CPC分类号： G11C14/009 , G11C13/0004 , G11C14/0072 , H01L27/101 , H03K3/356008
摘要： A method of driving a non-volatile flip-flop circuit comprising a first inverter (INV1) coupled to a first memory node (9) and a second memory node (10), a second inverter (INV2) coupled to the second memory node (10) and the first memory node (9), a first pass transistor (5), a second pass transistor (6), a first switching element for control (7) and a first variable resistor element (15) which are connected serially to each other and are connected between the first memory node (9) and a plate line (18), and a second switching element for control (8) and a second variable resistor element (16) which are connected serially to each other and are connected between the second memory node (10) and the plate line (18), wherein the resistance values of the first and second variable resistor elements (15, 16) can be changed by the heat generated by a current.
摘要翻译：一种驱动非易失性触发器电路的方法，包括耦合到第一存储器节点（9）和第二存储器节点（10）的第一反相器（INV1），耦合到第二存储器节点 10）和第一存储器节点（9），第一传输晶体管（5），第二传输晶体管（6），用于控制的第一开关元件（7）和第一可变电阻元件（15），其串联连接到彼此连接并且连接在第一存储节点（9）和板线（18）之间，以及用于控制的第二开关元件（8）和第二可变电阻元件（16），它们彼此串联连接并被连接在第二存储节点（10）和板线（18）之间，其中可以通过由电流产生的热量来改变第一和第二可变电阻元件（15,16）的电阻值。

10. 发明授权

US06847071B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06847071B2
公开(公告)日：2005-01-25
申请号：US10161696
申请日：2002-06-05
申请人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
发明人： Michihito Ueda , Kenji Toyoda , Kiyoyuki Morita , Takashi Ohtsuka
IPC分类号： H01L27/10 , G11C27/00 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C27/005 , G11C11/54 , H01L2924/0002 , H01L2924/00
摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.
摘要翻译：在电位产生装置中，N型MIS晶体管的源极相互连接到P型MIS晶体管的源极，并且还连接到输出端子。 N型MIS晶体管54的漏极连接到用于提供电源电压VDD的电源电压供应部分，并且P型MIS晶体管的漏极连接到地。此外，N型MIS晶体管的衬底电位为接地电压VSS，P型MIS晶体管56的衬底电位为电源电压VDD。因此，它构成为用于从源极输出的源极跟随器电路。通过利用该电位产生装置可以获得用于在NOR操作和NAND操作之间稳定切换的逻辑变换电路。

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