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1. 发明授权

US06604229B2 Method of designing wiring for power sources in a semiconductor chip, and a computer product 有权
公开(公告)号：US06604229B2
公开(公告)日：2003-08-05
申请号：US09812552
申请日：2001-03-21
申请人： Kenji Suzuki , Koji Banno , Toru Osajima , Takashi Yoneda , Takanori Nawa , Koji Tsuneto , Masuo Inui , Hiroyuki Yamamoto
发明人： Kenji Suzuki , Koji Banno , Toru Osajima , Takashi Yoneda , Takanori Nawa , Koji Tsuneto , Masuo Inui , Hiroyuki Yamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

2. 发明授权

US06622293B1 Method and system for designing wire layout without causing antenna error 有权
标题翻译：用于设计线路布局而不造成天线误差的方法和系统
公开(公告)号：US06622293B1
公开(公告)日：2003-09-16
申请号：US09711531
申请日：2000-11-14
申请人： Kenji Suzuki , Koji Banno , Toru Osajima
发明人： Kenji Suzuki , Koji Banno , Toru Osajima
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block includes the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.
摘要翻译：一种确定半导体器件中的电路布线的方法，包括每个对应于电路块的多个模块，包括以下步骤：在同一单层中提供待连接在一起的模块的模块端子，确定连接到通过在不高于单层的一个或多个层中布置导线，并且通过在一个或多个层中布置模块间导线来确定在模块端子之间连接的模块间线路的布局，模块端子在各个模块内部层不高于单层。

3. 发明授权

US07146592B2 Integrated logic circuit and hierarchical design method thereof 有权
标题翻译：集成逻辑电路及其分层设计方法
公开(公告)号：US07146592B2
公开(公告)日：2006-12-05
申请号：US11042061
申请日：2005-01-26
申请人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
发明人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , G06F17/5068 , H01L2224/05554 , H03K19/17744 , H03K19/1778
摘要： Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.
摘要翻译：模块14至18设置在芯片10中，模块14包括沿着模块14的外围设置的多个外部缓冲单元20和设置在多个外部缓冲单元20内的内部电路21。通过外部缓冲电池20在内部电路21和外部电路之间进行信号的输入和输出。每个外部缓冲单元的输出级晶体管的尺寸大于内部电路21的晶体管尺寸。外部缓冲单元20具有驱动能力，用于通过芯片中具有模块布置区域的最大曼哈顿长度的导线直接驱动芯片内的晶体管。如果多个外部缓冲单元20的设置区域不够，则扩大模块的尺寸，或者重新分配模块的重新分配，使得多个外部缓冲单元20具有足够的设置面积。

4. 发明授权

US06924666B2 Integrated logic circuit and hierarchical design method thereof 失效
公开(公告)号：US06924666B2
公开(公告)日：2005-08-02
申请号：US10263071
申请日：2002-10-03
申请人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
发明人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , G06F17/5068 , H01L2224/05554 , H03K19/17744 , H03K19/1778
摘要： Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.

5. 发明申请

US20050128850A1 Integrated logic circuit and hierarchical design method thereof 有权
标题翻译：集成逻辑电路及其分层设计方法
公开(公告)号：US20050128850A1
公开(公告)日：2005-06-16
申请号：US11042061
申请日：2005-01-26
申请人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
发明人： Kenji Suzuki , Toru Osajima , Shogo Tajima , Shigenobu Satoh
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17736 , G06F17/5068 , H01L2224/05554 , H03K19/17744 , H03K19/1778
摘要： Modules 14 to 18 are disposed in a chip 10, and the module 14 includes a plurality of external buffer cells 20 disposed along the peripheral of the module 14, and an internal circuit 21 disposed inside the plurality of external buffer cells 20. Input and output of signals is made between the internal circuit 21 and the external circuit, through the external buffer cells 20. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit 21. The external buffer cells 20 have a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cells 20 is not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cells 20 have their sufficient disposed area.
摘要翻译：模块14至18设置在芯片10中，模块14包括沿着模块14的外围设置的多个外部缓冲单元20和设置在多个外部缓冲单元20内的内部电路21。通过外部缓冲电池20在内部电路21和外部电路之间进行信号的输入和输出。每个外部缓冲单元的输出级晶体管的尺寸大于内部电路21的晶体管尺寸。外部缓冲单元20具有驱动能力，用于通过芯片中具有模块布置区域的最大曼哈顿长度的导线直接驱动芯片内的晶体管。如果多个外部缓冲单元20的设置区域不够，则扩大模块的尺寸，或者重新分配模块的重新分配，使得多个外部缓冲单元20具有足够的设置面积。

6. 发明授权

US06885046B2 Semiconductor integrated circuit configured to supply sufficient internal current 失效
标题翻译：半导体集成电路配置为提供足够的内部电流
公开(公告)号：US06885046B2
公开(公告)日：2005-04-26
申请号：US10058005
申请日：2002-01-29
申请人： Kenji Suzuki , Toru Osajima
发明人： Kenji Suzuki , Toru Osajima
IPC分类号： G06F17/50 , H01L21/82 , H01L23/528 , H01L27/10
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/45 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/45124 , H01L2224/4847 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： A semiconductor integrated circuit includes pads, a first power supply I/O cell which is connected to an external pin through a corresponding one of the pads, and a second power supply I/O cell which is not connected to an external pin through a corresponding one of the pads, but receives power supply from the first power supply I/O cell.
摘要翻译：半导体集成电路包括焊盘，第一电源I / O单元，其通过相应的一个焊盘连接到外部引脚;以及第二电源I / O单元，其不通过相应的外部引脚连接到外部引脚其中一个焊盘，但从第一个电源I / O单元接收电源。

7. 发明授权

US06467070B2 Design support apparatus for semiconductor devices 失效
标题翻译：半导体器件设计支持设备
公开(公告)号：US06467070B2
公开(公告)日：2002-10-15
申请号：US09808344
申请日：2001-03-15
申请人： Sachi Kuroda , Toshiaki Sugioka , Toru Osajima , Shigenori Ichinose
发明人： Sachi Kuroda , Toshiaki Sugioka , Toru Osajima , Shigenori Ichinose
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.
摘要翻译：一种用于半导体器件的设计支持装置，其用于在设计时快速地布置用于减少来自半导体器件的电磁辐射的非逻辑单元。在这种用于半导体器件的设计支持装置中，布局部分对逻辑单元和布线图案进行布局以连接逻辑单元。在布局部分进行布局之后，排列位置检测部分检测作为不包含逻辑单元或禁止区域的位置的排列位置。非逻辑单元图形存储部分存储非逻辑单元图案。含有现场检测部分的禁止区域检测禁止区域的包含场地，作为仅包含禁止区域的场所。非逻辑单元布置部分在布置的位置上布置非逻辑单元。此外，非逻辑单元布置部分将禁止区域的禁止区域的布置与非逻辑单元图案进行比较，并且将非逻辑单元仅在彼此不冲突的位置排列。

8. 发明申请

US20100252830A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100252830A1
公开(公告)日：2010-10-07
申请号：US12818588
申请日：2010-06-18
申请人： Toru Osajima
发明人： Toru Osajima
IPC分类号： H01L23/544 , H01L21/71 , H01L23/488
CPC分类号： H01L24/06 , H01L22/32 , H01L23/5286 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0203 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/49175 , H01L2224/49431 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00
摘要： A first external connection terminal at a first row is disposed to position at upside of a first I/O cell, and a second external connection terminal at a second row is formed at upside of a boundary portion between two adjacent first I/O cells. Here, the first external connection terminal and the second external connection terminal are disposed to be separated for a predetermined distance so as not to have an overlapped portion with each other, and formed in an identical layer. According to the constitution, it is possible to prevent disadvantages such as characteristic deterioration of a semiconductor integrated circuit and accuracy deterioration of an electrical inspection.
摘要翻译：第一行的第一外部连接端子被设置为位于第一I / O单元的上侧，并且在第二行的第二外部连接端子形成在两个相邻的第一I / O单元之间的边界部分的上侧。这里，第一外部连接端子和第二外部连接端子被设置为彼此分离预定距离以不具有重叠部分，并且形成在相同的层中。根据该结构，能够防止半导体集成电路的特性恶化以及电气检查的精度劣化等缺点。

9. 发明授权

US06501106B1 Semiconductor integrated circuit device and method of producing the same 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US06501106B1
公开(公告)日：2002-12-31
申请号：US09454997
申请日：1999-12-06
申请人： Toru Osajima
发明人： Toru Osajima
IPC分类号： H01L2710
CPC分类号： H01L27/11807
摘要： A semiconductor integrated circuit device in which connections within and between logic unit cells can be efficiently made is provided. Logic unit cells each including a plurality of basic cells are extended in an X-direction. To form one logic unit cell, second-layer wiring regions for making connections within the logic unit cell are formed in the X-direction, i.e., the extending direction. If there are five Y-coordinate channels, the second-layer wiring regions are formed only at one Y-coordinate channel. Second-layer wiring regions for connecting logic unit cells are also formed in the X-direction, and can be situated at any of the remaining four Y-coordinate channels.
摘要翻译：提供了可以有效地制造逻辑单元电池内和之间的连接的半导体集成电路器件。每个包括多个基本单元的逻辑单位单元在X方向上延伸。为了形成一个逻辑单元，在X方向，即延伸方向上形成用于在逻辑单元单元内进行连接的第二层布线区域。如果存在五个Y坐标通道，则仅在一个Y坐标通道处形成第二层布线区域。用于连接逻辑单元单元的第二层布线区域也在X方向上形成，并且可以位于剩余的四个Y坐标通道中的任一个处。

10. 发明授权

US06207980B1 Layout method of a semiconductor device 有权
标题翻译：半导体器件布局方法
公开(公告)号：US06207980B1
公开(公告)日：2001-03-27
申请号：US09241847
申请日：1999-02-02
申请人： Hiroshi Miyazaki , Kouji Tsunetou , Toru Osajima
发明人： Hiroshi Miyazaki , Kouji Tsunetou , Toru Osajima
IPC分类号： H01L2710
CPC分类号： H01L27/11898 , H01L23/528 , H01L24/06 , H01L2224/05553 , H01L2224/49175 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device includes multi-pin I/O buffers. The I/O buffers are located near an I/O pad area of the device. The multi-pin I/O buffers include multiple, generally L-shaped terminals that are connected to pads in the I/O pad area with wirings. The terminals of the I/O buffers include a horizontal terminal section and a vertical terminal section. The horizontal terminal sections extend in a width direction from a corner of the buffer toward a middle point of a side of the buffer, and the vertical terminal section extends in a length direction from the corner of the terminal toward a middle point of a side of the buffer. The wirings may also be generally L-shaped.
摘要翻译：半导体器件包括多引脚I / O缓冲器。 I / O缓冲区位于设备的I / O焊盘区域附近。多引脚I / O缓冲器包括多个通常为L形的端子，其通过布线连接到I / O焊盘区域中的焊盘。 I / O缓冲器的端子包括水平端子部分和垂直端子部分。水平端子部分在宽度方向上从缓冲器的角部朝向缓冲器的一侧的中点延伸，并且垂直端子部分在从端子的拐角到中间点的长度方向上延伸缓冲区。布线也可以是大致L形。

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