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    • 1. 发明申请
    • NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS CAPABLE OF MULTIPLE STORE OPERATIONS
    • 非易失性存储器利用多个存储器操作的MIS存储器晶体管
    • US20090016105A1
    • 2009-01-15
    • US11775951
    • 2007-07-11
    • Kenji NODATakashi KIKUCHI
    • Kenji NODATakashi KIKUCHI
    • G11C11/34G11C16/04
    • G11C14/00G11C11/412
    • A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.
    • 非易失性半导体存储器件包括:锁存器,被配置为存储数据,多个字线,被配置为激活多个字线中的一个字线的驱动器;以及耦合到各个字线的多个非易失性存储器单元,每个非易失性存储器件 存储器单元耦合到所述锁存器,以便在激活相应的一条字线时与所述锁存器交换存储的数据,所述非易失性存储器单元中的每一个包括两个MIS晶体管,并且被配置为将数据存储为晶体管特性的不可逆变化, 两个MIS晶体管中的一个,其中驱动器包括至少一个非易失性存储单元,其存储响应于多次数据存储的数量的计数数据,并且被配置为激活多个非易失性存储单元中的一个, 字数由计数数据表示。
    • 2. 发明申请
    • NONVOLATILE MEMORY UTILIZING MIS MEMORY TRANSISTORS WITH FUNCTION TO CORRECT DATA REVERSAL
    • 非易失性存储器利用功能正确数据转换的MIS记忆体晶体管
    • US20090213664A1
    • 2009-08-27
    • US12037414
    • 2008-02-26
    • Takashi KIKUCHIKenji NODA
    • Takashi KIKUCHIKenji NODA
    • G11C7/00
    • G11C7/1045G11C7/1006G11C7/12G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.
    • 非易失性半导体存储器件包括具有两个节点的锁存电路,包括两个MIS晶体管的非易失性存储器单元,配置成在第一操作模式期间在两个节点和两个MIS晶体管之间提供直连接并提供交叉连接 在第二操作模式期间在两个节点和两个MIS晶体管之间,以及控制电路,被配置为在第一和第二操作模式之一中使得非易失性存储单元将锁存在锁存电路中的数据存储为不可逆变化 的晶体管特性出现在所述两个MIS晶体管中的所选择的一个中,并且还被配置为在所述第一和第二操作模式中的另一个中引起所述锁存电路来检测存储在所述非易失性存储单元中的数据。
    • 4. 发明申请
    • CYLINDER APPARATUS
    • 气缸装置
    • US20100301578A1
    • 2010-12-02
    • US12785671
    • 2010-05-24
    • Kenji NODAYoshiaki Totani
    • Kenji NODAYoshiaki Totani
    • B60G21/10F01B11/02
    • F16F9/3257B60G21/0558F16F9/3242F16F9/325
    • A piston coupled to a piston rod is inserted in a cylinder, and an outer cylinder is disposed around the cylinder so as to define a reservoir therebetween. A separator tube is disposed around the cylinder so as to define an annular passage therebetween. The piston rod is locked and unlocked so that a movement of the piston is prevented and allowed, by closing and opening an electromagnetic open/close valve so as to block and allow a flow of hydraulic fluid through a flow passage between the annular passage and the reservoir. The separator tube has a greater thickness. O-rings are disposed so as to provide seals between the separator tube and the cylinder. The separator tube extends to positions such that the ends of the separator tube overlap a base valve and a rod guide, thereby holding the respective ends of the cylinder. Due to this configuration, it is possible to prevent deformation of the cylinder and the separator tube due to an increase in the hydraulic pressure, and improve the pressure resistance.
    • 联接到活塞杆的活塞插入到气缸中,并且外筒围绕气缸设置以在其间限定一个容器。 分隔管设置在圆筒周围,以便在它们之间限定环形通道。 活塞杆被锁定和解锁,从而通过关闭和打开电磁开/关阀来阻止和允许活塞的运动,以阻止和允许液压流体流过环形通道和 水库 分离管具有更大的厚度。 O形环被设置成在分离器管和气缸之间提供密封。 分离管延伸到使得分离管的端部与基座阀和杆引导件重叠的位置,从而保持气缸的相应端部。 由于这种构造,可以防止由于液压的增加导致的气缸和分离管的变形,并提高耐压性。
    • 5. 发明申请
    • MIS-TRANSISTOR-BASED NONVOLATILE MEMORY
    • 基于MIS-TRANSISTOR的非易失性存储器
    • US20090213650A1
    • 2009-08-27
    • US12036938
    • 2008-02-25
    • Kenji NODA
    • Kenji NODA
    • G11C11/40
    • G11C14/00G11C14/0063
    • A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.
    • 一种非易失性半导体存储器件,包括:锁存电路,包括第一反相器和彼此交叉耦合的第二反相器,第一反相器的MIS晶体管的源极节点和第二反相器的MIS晶体管的源极节点都耦合 以及控制电路,其被配置为在存储模式下向所述板线施加第一电位,以引起对所述MIS晶体管之一的阈值电压的改变,并且被配置为向所述板线施加第二电位 电源接通模式,以使得锁存电路根据在存储模式下产生的阈值电压的变化来锁存数据,使得由电源接通模式中的锁存电路锁存的数据自动输出到非易失性半导体存储器件外部 上电时。