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1. 发明授权

US5377339A Computer for simultaneously executing instructions temporarily stored in a cache memory with a corresponding decision result 失效
标题翻译：用于同时执行临时存储在具有相应决定结果的高速缓冲存储器中的指令的计算机
公开(公告)号：US5377339A
公开(公告)日：1994-12-27
申请号：US191069
申请日：1994-02-03
申请人： Mitsuo Saito , Kenji Minagawa , Takeshi Aikawa
发明人： Mitsuo Saito , Kenji Minagawa , Takeshi Aikawa
IPC分类号： G06F9/38 , G06F12/08 , G06F15/16 , G06F9/00
CPC分类号： G06F9/382 , G06F9/3808 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructions and a corresponding decision result are stored in the cache memory. The decision process is performed for several groups of the plural instructions read out from the main memory to the cache memory in order. Then, the plural instructions are respectively assigned to a corresponding operation unit according to the decision result, and are subsequently executed by the corresponding operation unit. As a result of this arrangement, the repeated decision process for the plural instructions is not necessary when they are later read out from the cache memory to the operation unit.
摘要翻译：当从主存储器向高速缓冲存储器读出指令时，用于同时执行多个指令的计算机决定多种指令的操作种类和同时执行的可能性。多个指令和相应的判定结果存储在高速缓冲存储器中。对从主存储器读出的多组指令的顺序执行到高速缓冲存储器的决定处理。然后，根据判定结果将多个指令分别分配给对应的运算单元，并由随后的运算单元执行。作为这种布置的结果，当它们稍后从高速缓冲存储器读出到操作单元时，不需要多个指令的重复确定处理。

2. 发明授权

US5446849A Electronic computer which executes squash branching 失效
标题翻译：执行南瓜分支的电子计算机
公开(公告)号：US5446849A
公开(公告)日：1995-08-29
申请号：US799981
申请日：1991-11-29
申请人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
发明人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
IPC分类号： G06F9/38 , G06F12/10
CPC分类号： G06F12/1063 , G06F9/30072 , G06F9/3842 , G06F9/3859 , G06F12/1027
摘要： An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.
摘要翻译：根据本发明的电子计算机能够同时执行多个指令。其特征在于包括标志添加部分，用于判断多个指令中的每一个是延迟分支指令还是南瓜分支指令，并且基于该结果，向每个指令添加指示中止条件的标志，以及一个命令执行中止部分，用于根据添加到每个指令的标志是否指示中止条件和每个分支指令成立，中止每个指令的执行。

3. 发明授权

US5561774A Parallel processing type processor system with trap and stall control functions 失效
标题翻译：并行处理型处理器系统具有陷波和失速控制功能
公开(公告)号：US5561774A
公开(公告)日：1996-10-01
申请号：US291582
申请日：1994-08-16
申请人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
发明人： Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa , Kenji Takeda
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863 , G06F9/3885
摘要： A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.
摘要翻译：一种具有陷波和失速控制功能的并行处理型处理器系统，其能够在不增加周期时间的情况下进行操作，从而可以防止系统中的时钟频率的降低。在该系统中，处理器单元被控制，使得当在执行提供给处理器单元的至少一个指令的同时执行异常时，同时提供给处理器单元的所有指令的处理被中止。此外，当不可能在执行提供给处理器单元的指令的同时拒绝发生异常的可能性时，同时提供给处理器单元的指令的处理被停止。

4. 发明授权

US5617553A Computer system which switches bus protocols and controls the writing of a dirty page bit of an address translation buffer 失效
标题翻译：切换总线协议并控制写入地址转换缓冲区的脏页位的计算机系统
公开(公告)号：US5617553A
公开(公告)日：1997-04-01
申请号：US429103
申请日：1995-04-26
申请人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
发明人： Kenji Minagawa , Takeshi Aikawa , Mitsuo Saito
IPC分类号： G06F9/38 , G06F12/10 , G06F9/06
CPC分类号： G06F12/1063 , G06F9/30072 , G06F9/3842 , G06F9/3859 , G06F12/1027
摘要： An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer includes an address buffer translator which translates a virtual address to a physical address and produces a bus protocol specifying signal. A bus interface changes bus protocols in accordance with the bus protocol specifying signal in order to permit a transfer of a physical address and data on the bus. In another embodiment, when the data in a cache memory is changed, a dirty bit for the cache memory is set but a corresponding dirty bit in the address translation buffer is not changed until a copy-back operation from the cache memory to a main memory occurs. The dirty page bit of the address translation buffer is changed utilizing software.
摘要翻译：一种电子计算机，其使用不同的总线协议来传送用于处理器到处理器通信和处理器到外设通信的信息。电子计算机包括地址缓冲器翻译器，其将虚拟地址转换为物理地址并产生总线协议指定信号。总线接口根据总线协议指定信号改变总线协议，以允许在总线上传送物理地址和数据。在另一个实施例中，当高速缓冲存储器中的数据被改变时，设置高速缓冲存储器的脏位，但地址转换缓冲器中相应的脏位不改变，直到从高速缓冲存储器到主存储器的复制操作发生。使用软件更改地址转换缓冲区的脏页位。

5. 发明授权

US5371865A Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand 失效
标题翻译：具有主存储器和高速缓冲存储器的计算机，用于使用基地址和偏移操作数的阵列数据预加载操作
公开(公告)号：US5371865A
公开(公告)日：1994-12-06
申请号：US715932
申请日：1991-06-14
申请人： Takeshi Aikawa , Kenji Minagawa , Mitsuo Saito
发明人： Takeshi Aikawa , Kenji Minagawa , Mitsuo Saito
IPC分类号： G06F9/38 , G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6028
摘要： A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.
摘要翻译：一种具有用于存储多个数据的主存储器的计算机，用于临时存储多个数据的一部分的高速缓冲存储器，用于访问存储在高速缓冲存储器中的数据的处理器，并根据指令处理该数据。处理器具有与预加载指令相结合的访问指令以及仅用于访问数据的访问指令，并且包括当处理器根据与高速缓冲存储器中的访问指令相结合从高速缓存存储器访问数据时向高速缓存存储器指示预载条件的指示器电路预加载指令。当处理器指示预加载条件时，高速缓冲存储器预先从主存储器预处理器接下来要访问的数据。

6. 发明授权

US5276821A Operation assignment method and apparatus therefor 失效
标题翻译：操作分配方法及其设备
公开(公告)号：US5276821A
公开(公告)日：1994-01-04
申请号：US579958
申请日：1990-09-10
申请人： Toru Imai , Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa
发明人： Toru Imai , Takeshi Aikawa , Mitsuo Saito , Kenji Minagawa
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F8/445
摘要： According to an assigning method and its apparatus having a resource use recording section for recording a use state of a resource necessary for executing given operations, a functional unit possession recording section for recording information representing an inexecution functional unit, and an operator information management section for storing an operation executable by each functional unit and a clock count necessary for executing the operation, in order to assign an operation selected from the operations (by the operation selection step) to an optimal functional unit, the use state of the resource is checked from the resource use recording section (with reference to the usable resource decision step), the operation executable functional unit is found from the operation unit possession recording section (by the operation assignable unit decision step). A clock count necessary for executing the operation in the executable functional unit is considered with reference to the operator information management section. The optimal functional unit to be assigned with the selected operation is selected and decided (finally by the functional unit selection step), thereby performing an effective operation assigning process.
摘要翻译：根据分配方法及其装置，具有用于记录执行给定操作所需的资源的使用状态的资源使用记录部分，用于记录表示不执行功能单元的信息的功能单元占有记录部分，以及用于存储每个功能单元可执行的操作和执行该操作所需的时钟计数，以便将从操作（通过操作选择步骤）中选择的操作分配给最佳功能单元，从资源的使用状态检查资源的使用状态资源使用记录部（参照可用资源决定步骤），从操作部拥有记录部（通过操作分配部判定步骤）找到操作执行功能部。参考操作者信息管理部分考虑执行可执行功能单元中的操作所需的时钟计数。选择并确定要分配给所选择的操作的最佳功能单元（最后通过功能单元选择步骤），从而执行有效的操作分配处理。

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